MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 131

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

5.3.1.24
The Out Clock 1 clock config register is shown in
OUT1CCR.
Freescale Semiconductor
OUT0_CLK_SR
Address: Base + 0x70
Address: Base + 0x74
OUT0_DIV
OUT0_EN
Reset
Reset
Reset
Reset
Field
W
W
W
W
R
R OUT0_CLK_
C
R
R OUT1_CLK_
16
16
1
0
1
0
0
0
SRC
SRC
Out Clock 1 Config Register (OUT1CCR)
OUT0 divider Ratio
A value of 0x0000 bypasses the divider.
Note: This value can only be changed when the value of OUT0_EN equals 0
OUT0 Divider Enable
0 OUT0 divider is disabled.
1 OUT0 divider is enabled.
Out Clock 0 Clock Source
00 From SYS_CLK.
01 From REF_CLK.
10 From PSC_MCLK_IN.
11 From CAN_CLK_IN.
17
17
1
0
1
0
1
1
f
out0_clk
18
18
1
0
0
1
0
0
2
2
Figure 5-28. Out Clock 0 Clock Config Register (OUT0CCR)
Figure 5-29. Out Clock 1 Clock Config Register (OUT1CCR)
= f
out0_clk_src
19
19
1
0
0
1
0
0
3
3
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 5-28. OUT0CCR field descriptions
20
20
4
1
0
0
4
1
0
0
/ (OUT0_DIV + 1)
21
21
1
0
0
1
0
0
5
5
22
22
1
0
0
1
0
0
6
6
OUT0_DIV
OUT1_DIV
Figure
23
23
1
0
0
1
0
0
7
7
Description
5-29.
24
24
8
1
0
0
8
1
0
0
Table 5-29
25
25
9
1
0
0
9
1
0
0
10
26
10
26
1
0
0
1
0
0
defines the bit fields of
11
27
11
27
1
0
0
1
0
0
Clocks and Low-Power Modes
12
28
12
28
1
0
0
1
0
0
Access: User read/write
Access: User read/write
13
29
13
29
1
0
0
1
0
0
14
30
14
30
1
0
0
1
0
0
OUT0
OU1_
_EN
EN
15
31
15
31
5-31
0
0
0
0
0
0