MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 449

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chapter 18
Integrated Programmable Interrupt Controller (IPIC)
18.1
This chapter describes the IPIC interrupt protocol, various types of interrupt sources controlled by the IPIC
unit, and the IPIC registers with some programming guidelines. The MPC5125 IPIC unit prioritizes and
manages interrupts from the following controller units:
The interrupt sources controlled by the IPIC unit cause exceptions in the processor core. The internal
interrupt signal (int) is the main interrupt output from the IPIC to the Power Architecture core and causes
the regular interrupt exception. The cint signal is the critical interrupt output from the IPIC to the e300 core
and causes the critical interrupt exception. The smi signal is the system management interrupt output from
the IPIC to the Power Architecture core and causes the system management interrupt exception. The
machine check exception is caused by the internal mcp signal generated by the IPIC, informing the host
processor of error conditions, assertion of the external IRQ0 machine-check request (enabled when
IPIC_SEMSR[SIRQ0] = 1), and other conditions.
Freescale Semiconductor
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DDR memory controller (DDR)
LocalPlus controller (LPC)
Two ethernet controllers (FEC)
Ten programmable serial controllers (PSC)
Two USB ULPI controllers (USB)
NAND Flash controller (NFC)
System bus arbiter (SBA)
Real time clock timer (RTC)
Sixteen Global Timers (GPT)
Software Watchdog timer (WDT)
I
Controller Area Network (CAN)
Byte Data Link controller (BDLC)
Display Interface Unit (DIU)
Secure Digital Host controller (SDHC)
Direct Memory Access (DMA2)
Power Management controller (PMC)
General-purpose IO controller (GPIO)
PSC FIFO controller (FIFOC)
Temperature Sensor (TEMP)
IC Identification (IIM)
2
C controllers (I
Introduction
2
C)
MPC5125 Microcontroller Reference Manual, Rev. 2
18-1