MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 89

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.2
During the power-up sequence the PORESET pin must be asserted by an external device for a minimum
of 32 XTAL clock cycles. The oscillator input (XTALI) must be stable prior to PORESET de-assertion.
The reset configuration word is latched on the de-assertion of Power On Reset. After PORESET has been
qualified, the HRESET flow is started.
4.3
HRESET provides a mechanism to initialize all clocks and peripherals to their initial values. The CPMF
and SPMF bits, which set the feedback ratio for the Core and System PLLs, are not affected by HRESET.
The reset configuration word is sampled only when the PORESET is deasserted.
4.3.1
The following sources may initiate an HRESET sequence:
4.3.2
When a HRESET sequence is initiated, the following occurs:
1. Checkstop may be initiated when the e300 core enters the checkstop state. This state may be masked in the RESET module,
2. The reset configuration register in the RESET module may initiate either a SRESET or HRESET sequence.
3. The RTC timer mechanism retains state as long as V
Freescale Semiconductor
e300 core or IPIC.
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PORESET input signal
HRESET input signal
Watchdog timer (WDT) module
JTAG command
Bus monitor
Checkstop event
PLL unlock event
Software write to the RESET module
HRESET pin is asserted by the device
SRESET pin is asserted by the device.
MSR[IP] bit in the e300 core is updated to reflect the vector table location
PLLs reload programming information requiring the PLL re-lock to the reference clock signal
Clock dividers are initialized
Memory map initializes to reset state
All peripheral logic asserts reset unless otherwise noted
Reset source is captured in the RESET module
The e300 core starts fetching instructions from the vector indicated by the RST_CONF word
(PORESET) Power-On Initialization
HRESET Flow
Sources
Impacts
1
MPC5125 Microcontroller Reference Manual, Rev. 2
2
bat
provides power to the RTC module
3
Reset
4-3