MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 396

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Fast Ethernet Controller (FEC)
14.6
serial interface for 10 Mbit/s Ethernet. The interface mode is selected by the MII_MODE and
RMII_MODE bit in the ETH_R_CNTRL register. In MII mode, (ETH_R_CNTRL[MII_MODE] = 1,
ETH_R_CNTRL[RMII_MODE] = 0), there are 18 signals defined by the 802.3 standard and supported by
the EMAC.
14-40
Note: After the software driver has set up the buffers for a frame, it should set up the corresponding BDs. The last step in setting
Each FEC supports an MII interface and reduced MII interface for 10/100 Mbit/s Ethernet and a 7-wire
Transmit
Pointer
Length
Buffer
Field
ABC
Data
Date
TO1
TO2
TC
W
R
L
up the BDs for a transmit frame should be to set the r bit in the first BD for the frame. The driver should follow that with a
write to ETH_X_DES_ACTIVE, which triggers the FEC to poll the next BD in the ring.
Ready, written by FEC and user.
0 The data buffer associated with this BD is not ready for transmission. You are free to manipulate this BD or its
1 The data buffer that was prepared for transmission has not been transmitted, or is currently being transmitted. No
Transmit software ownership bit.
This field is reserved for use by software. This read/write bit must not be modified by hardware. Its value does not
affect hardware.
Wrap, written by user.
This field is reserved for use by software. This read/write bit must not be modified by hardware. Its value does not
affect hardware.
0 The next buffer descriptor is found in the consecutive location.
1 The next buffer descriptor is found at the location defined in ETH_X_DES_START.
Transmit software ownership bit
This field is reserved for use by software. This read/write bit must not be modified by hardware. Its value does not
affect hardware.
Last in frame, written by user.
0 The buffer is not the last in the transmit frame.
1 The buffer is the last in the transmit frame.
TX CRC, written by user (only valid if L equals 1).
0 End transmission immediately after the last data byte.
1 Transmit the CRC sequence after the last data byte.
Append bad CRC, written by user (only valid if l = 1)
0 No effect.
1 Transmit an invalid CRC sequence after the last data byte (regardless of TC value).
Data length, written by user.
Data length is the number of octets the FEC should transmit from this BD’s data buffer. It is never modified by the
FEC. Bits [21:31] are used by the DMA engine. Bits [16:20] are ignored.
TX buffer pointer, written by user.
The transmit buffer pointer, which contains the address of the associated data buffer, must always be evenly divisible
by 4. The buffer must reside in memory external to the FEC. This value is never modified by the Ethernet controller.
Network Interface Options
associated data buffer. The FEC clears this bit after the buffer has been transmitted or after an error condition is
encountered.
fields of this BD may be modified after this bit is set.
Table 14-34
shows these.
Table 14-33. Transmit Buffer Field Descriptions
MPC5125 Microcontroller Reference Manual, Rev. 2
Description
Freescale Semiconductor