MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 398

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Fast Ethernet Controller (FEC)
Table 14-36. 7-Wire Interface (continued)
Signal Description
FEC signal name
Receive enable
FECn_RX_DV/RMII_CRS_DV
Receive data
FECn_RXD_0/RMII_RX0
14.6.1
FEC Frame Transmission
The Ethernet transmitter is designed to work with almost no intervention from software. After
ETHER_EN is asserted and data appears in the transmit FIFO, the Ethernet MAC is able to transmit onto
the network.
When the transmit FIFO fills to the watermark (defined by the ETH_X_WMRK register), the MAC
transmit logic asserts TX_EN and starts transmitting the preamble sequence, the start frame delimiter, and
then the frame information from the FIFO. However, the controller defers the transmission if the network
is busy (carrier sense is asserted). Before transmitting, the controller waits for carrier sense to become
inactive, and then determines if carrier sense stays inactive for 60 bit times. If so, then the transmission
begins after waiting an additional 36 bit times (96 bit times after carrier sense originally became inactive).
If a collision occurs during transmission of the frame (half-duplex mode), the Ethernet controller follows
the specified backoff procedures and attempts to retransmit the frame until the retry limit threshold is
reached. The transmit FIFO stores at least the first 64 bytes of the transmit frame, so the first 64 bytes do
not have to be retrieved again from system memory in case of a collision. This improves bus utilization
and latency in case immediate retransmission is necessary.
When all the frame data has been transmitted, the FCS (32-bit CRC) bytes are appended if the TC bit is
set in the transmit frame control word. If the ABC bit is set in the transmit frame control word, a bad CRC
is appended to the frame data regardless of the TC bit value. Following the transmission of the CRC, the
Ethernet controller writes the frame status information to the MIB block. Short frames are automatically
padded by the transmit logic (if the TC bit in the transmit buffer descriptor for the end-of-frame buffer
equals 1).
Both buffer (TXB, FEC only) and frame (TFINT, FEC) interrupts may be generated as determined by the
settings in the ETH_IMASK register.
Transmit error interrupts are HBERR, BABT, LATE_COL, COL_RETRY_LIM, XFIFO_UN and
XFIFO_ERROR. If the transmit frame length exceeds MAX_FL bytes, the BABT interrupt is asserted;
however, the entire frame is transmitted (no truncation).
To pause transmission, set the graceful transmit stop (GTS) bit in the ETH_X_CNTRL register. When the
GTS is set, the FEC transmitter stops immediately if transmission is not in progress; otherwise, it continues
transmission until the current frame finishes or terminates with a collision. After the transmitter has
stopped, the GRA interrupt is asserted. If GTS is cleared, the FEC resumes transmission with the next
frame.
The Ethernet controller transmits bytes least significant bit (LSB) first.
MPC5125 Microcontroller Reference Manual, Rev. 2
14-42
Freescale Semiconductor