MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 238

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Direct Memory Access (DMA)
contents of DMAEEIH and DMAEEIL registers to be set to 1s. Reads of this register return all 0s. See
Figure 9-9
9.2.1.8
The DMA Clear Enable Error Interrupt (DMACEEI) register provides a simple memory-mapped
mechanism to clear a given bit in the DMAERQH and DMAERQL registers to disable the error interrupt
for a given channel. The data value on a register write causes the corresponding bit in the DMAERQH or
DMAERQL register to be cleared. A data value of 64 to 127 (regardless of the number of implemented
channels) provides a global clear function, forcing the entire contents of the DMAERQH and DMAERQL
to be cleared, disabling all DMA request inputs. Reads of this register return all 0s. See
Table 9-11
9-18
Address: Base + 0x001A
Address: Base + 0x001B
CEEI[6:0]
SEEI[6:0]
Reset
Reset
Field
Field
W
W
R
R
and
for the DMACEEI definition.
DMA Clear Enable Error Interrupt (DMACEEI)
Set Enable Error Interrupt
0–63
64–127 Sets all the bits in the DMAEEIH and DMAEEIL registers.
Clear Enable Error Interrupt
0–63
64–127 Clear all the bits in the DMAERQH and DMAERQL registers.
Table 9-10
0
0
0
0
0
0
Figure 9-10. DMA Clear Enable Error Interrupt Register (DMACEEI)
Figure 9-9. DMA Set Enable Error Interrupt Register (DMASEEI)
Sets the corresponding bit in the DMAEEIH or DMAEEIL register. For example, writing a value of
0b000_1111 (15 d, 0xF) sets the bit for EEI15 in DMAEEIL, allowing the assertion of an error signal
on channel 15 to generate an error interrupt request.
Clears the corresponding bit in the DMAERQH or DMAERQL register.
for the DMASEEI definition.
1
0
0
1
0
0
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 9-10. DMASEEI field descriptions
Table 9-11. DMACEEI field descriptions
0
0
0
0
2
2
0
0
0
0
3
3
Description
Description
SEEI[6:0]
CEEI[6:0]
0
0
0
0
4
4
0
0
0
0
5
5
Freescale Semiconductor
Access: User read/write
Access: User read/write
0
0
0
0
6
6
Figure 9-10
0
0
0
0
7
7
and