MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 954

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Universal Serial Bus Interface with On-The-Go
32-126
Conditio
not(A)
not(D)
not(C)
not(B)
not(D)
•
•
•
•
•
•
C
C
n
A
A
A
B
DATA0/1. This response may only occur for an IN endpoint. The number of bytes received is
added to the accumulated byte count in QH[S-bytes]. The state of the transfer is advanced by the
result and the host controller exits this state for this queue head.
Advancing the transfer state may cause other processing events such as retirement of the qTD and
advancement of the queue.
If the data sequence PID does not match the expected, the entirety of the data received in this split
transaction is ignored, the transfer state is not advanced, and this state is exited.
NAK. The target endpoint Nak'd the full- or low-speed transaction. The state of the transfer is not
advanced, and this state is exited. The host controller must reload Cerr with maximum value on
this response.
ERR. There was an error during the full- or low-speed transaction. The ERR status bit is set, Cerr
is decremented, the state of the transfer is not advanced, and this state is exited.
STALL. The queue is halted (an exit condition of the Execute Transaction state). The status field
bits:
Active bit is cleared and the Halted bit is set and the qTD is retired. Responses not enumerated in
the list or received out of sequence are illegal and may result in undefined host controller behavior.
The other possible combinations of tests A, B, C, and D may indicate data or response was lost.
Table 32-76
Ignore QHD
If PIDCode = IN
Halt QHDIf PIDCode = OUT
Retry start-split
If PIDCode = IN
Halt QHD
If PIDCode = OUT
Retry start-split
Execute complete-split
Table 32-76. Interrupt IN/OUT Do Complete Split State Execution Criteria
Action
lists the possible combinations and the appropriate action.
MPC5125 Microcontroller Reference Manual, Rev. 2
Neither a start nor complete-split is scheduled for the current micro-frame. Host
controller should continue walking the schedule.
Progress bit check failed. These means a complete-split has been missed. There is
the possibility of lost data. If PID Code is an IN, the queue head must be halted. If PID
code is an OUT, the transfer state is not advanced and the state exited (for example,
start-split is retried). This is a host-induced error and does not affect Cerr. In either
case, set the missed micro-frame bit in the status field to a one.
QH.FrameTag test failed. This means that exactly one or more H-Frames have been
skipped. This means complete-splits and have missed. There is the possibility of lost
data. If PID Code is an IN, then the Queue head must be halted.If PID Code is an
OUT, the transfer state is not advanced and the state exited (for example, start-split
is retried). This is a host-induced error and does not affect Cerr. In either case, set the
missed micro-frame bit in the status field to a one.
This is the non-error case where the host controller executes a complete-split
transaction.
Description
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