MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 405

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

14.6.4
Full-duplex flow control allows you to transmit pause frames and to detect received pause frames. Upon
detection of a pause frame, MAC data frame transmission stops for a given pause duration.
To enable pause frame detection, the FEC must operate in full-duplex mode (ETH_X_CNTRL[FDEN] set)
and flow control enable (ETH_R_CNTRL[FCE]) must be set. The FEC detects a pause frame when the
fields of the incoming frame match the pause frame specifications, as shown in
the receive status associated with the frame should indicate that the frame is valid.
Pause frame detection is performed by the receiver and descriptor controller modules. The descriptor
controller runs an address recognition subroutine to detect the specified pause frame destination address,
while the receiver detects the type and opcode pause frame fields. On detection of a pause frame, graceful
transmit stop is asserted by the FEC internally. When transmission has paused, the graceful stop complete
(GRA) interrupt is asserted and the pause timer begins to increment. The pause timer makes use of the
transmit backoff timer hardware, which is used for tracking the appropriate collision backoff time in
half-duplex mode. The pause timer increments once every slot time, until pause_duration slot times have
expired. When pause_duration expires, graceful transmit stop is deasserted, allowing MAC data frame
transmission to resume. The receive flow control pause (RFC_PAUSE) status bit is asserted while the
transmitter is paused due to reception of a pause frame.
To transmit a pause frame, the FEC must operate in full-duplex mode and software must assert flow control
pause (TFC_PAUSE). On assertion of TFC_PAUSE, the transmitter asserts graceful transmit stop
internally. When the transmission of data frames stops, the graceful stop complete (GRA) interrupt asserts.
Following GRA assertion, the pause frame is transmitted. When pause frame transmission is complete,
TFC_PAUSE and graceful transmit stop are deasserted internally.
During pause frame transmission, the transmit hardware places data into the transmit data stream from the
registers shown in
Specify the desired pause duration in the ETH_OP_PAUSE register.
Freescale Semiconductor
48-bit destination address
PAUSE Frame Fields
48-bit source address
16-bit pause duration
Full-Duplex Flow Control
16-bit opcode
16-bit type
Table
48-Bit Destination Address
48-bit source address
16-bit pause duration
14-39.
16-bit opcode
16-bit type
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 14-38. PAUSE Frame Field Specification
Table 14-39. Transmit Pause Frame Registers
{ETH_PADDR1[0:31], ETH_PADDR2[0:15]}
{FDXFC_DA1[0:31], fDXFC_DA2[0:15]}
ETH_OP_PAUSE[16:31]
ETH_OP_PAUSE[0:15]
ETH_PADDR2[16:31]
FEC Register
0x0180_C200_0001 or Physical Address
0x0000 to 0xFFFF
0x8808
0x0001
any
Table
0x0180_C200_0001
Register Contents
0x0000 to 0xFFFF
Fast Ethernet Controller (FEC)
Physical address
0x0001
14-38. In addition,
8808
14-49