MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 167

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Because a 0 dominates a 1, the message with the lowest value has the highest priority and always wins
arbitration. A message with priority 000 wins arbitration over a message with priority 011. This method
of arbitration works no matter how many bits of priority encoding are contained in the message.
6.4.2.11
The BDLC module detects several types of transmit and receive errors that can occur during the
transmission of a message onto the J1850 bus.
6.4.2.11.1
If the BDLC module is transmitting a message and the message received contains a symbol error, a framing
error, a bus fault, a BREAK symbol, or a logic 1 symbol when a logic 0 is being transmitted, this
constitutes a transmission error. Receiving a logic 0 symbol when transmitting a logic 1 is considered a
loss of arbitration condition (see
When a transmission error is detected, the BDLC module immediately ceases transmitting. Further
transmission or reception is disabled until a valid EOF symbol is detected on the J1850 bus. The error
condition is reflected by setting the symbol invalid or out of range flag in the BDLC_DLCBSVR register.
If the interrupt enable bit (IE in the BDLC_DLCBCR1 register) is set, an interrupt request from the BDLC
module is generated. Reading the BDLC_DLCBSVR register clears this flag.
6.4.2.11.2
A cyclical redundancy check (CRC) error is detected when the data bytes and CRC byte of a received
message are processed, and the CRC calculation result is not equal to 0xC4. The CRC code should detect
any single and 2 bit errors, as well as all 8 bit burst errors, and almost all other types of errors. The CRC
error flag in the BDLC_DLCBSVR register is set when a CRC error is detected. If the interrupt enable bit
(IE in the BDLC_DLCBCR1 register) is set, an interrupt request from the BDLC module is generated.
Reading the BDLC_DLCBSVR register clears this flag.
Freescale Semiconductor
Transmitter A
Transmitter B
J1850 Bus
J1850 Bus Errors
Transmission Error
CRC Error
Passive
Passive
Passive
Active
Active
Active
MPC5125 Microcontroller Reference Manual, Rev. 2
Figure 6-17. J1850 VPW Bitwise Arbitrations
Section 6.4.2.10.2, “Message
SOF
Data
Bit 1
0
0
0
Data
Bit 2
1
1
1
Data
Bit 3
1
1
1
Arbitration”) and not a transmission error.
1
Data
Bit 4
0
0
Data
Bit 5
0
0
Byte Data Link Controller (BDLC)
Transmitter A detects
an active state on the bus
and stops transmitting.
arbitration and continues
Transmitter B wins
transmitting.
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