MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 466

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Integrated Programmable Interrupt Controller (IPIC)
18.2.1.8
Each implemented bit in the IPIC_SIMSR_H and IPIC_SIMSR_L, shown in
Figure
corresponding IPIC_SIMSRx bit. When an interrupt request occurs, the corresponding IPIC_SIPNRx bit
is set, regardless of the IPIC_SIMSRx bit. However, if the corresponding IPIC_SIMSRx bit is cleared, no
interrupt request is passed to the core.
When the IPIC_SIMSRx bit is cleared by the user at the same time an interrupt source requests an interrupt
service, the request stops. If the user sets the IPIC_SIMSRx bit later, a previously pending interrupt request
is processed by the core according to its assigned priority.
18-18
Address: Base + 0x20
SYSD1P–
Reset
Reset
SYSD0P
SYSD7P
Field
W
W
R
R GPT1
18-11, corresponds to an internal interrupt source. The user masks an interrupt by clearing the
PSC4 PSC5 PSC6 PSC7 PSC8 PSC9 GPT8 GPT9
16
0
0
0
0
System Internal Interrupt Mask Register (IPIC_SIMSR_H and
IPIC_SIMSR_L)
GPT1
SYSD0 Priority order. Defines which interrupt source asserts its request in the SYSD0 priority position. The
user should not program the same code to more than one priority position (0–7). These bits can be changed
dynamically. The definition of SYSD0P is shown as follows:
000 I2C1 asserts its request in the SYSD0 position.
001 I2C2 asserts its request in the SYSD0 position.
010 I2C3 asserts its request in the SYSD0 position.
011 MSCAN1 asserts its request in the SYSD0 position.
100 MSCAN2 asserts its request in the SYSD0 position.
101 BDLC asserts its request in the SYSD0 position.
110 GPT0 asserts its request in the SYSD0 position.
111 GPT1 asserts its request in the SYSD0 position.
Same as SYSD0P, but for SYSD1P–SYSD7P.
Figure 18-10. System Internal Interrupt Mask High Register (IPIC_SIMSR_H)
17
0
1
0
1
SDH
C2
18
0
0
2
FEC1 FEC2 NFC
19
0
0
3
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 18-10. IPIC_SIPRR_D field descriptions
20
4
0
0
21
0
0
5
LPC
22
0
0
6
SDH
C1
23
0
0
7
Description
FIFO
I2C1
24
C
8
0
0
I2C2
25
9
0
0
0
I2C3
10
26
0
0
0
OTG1
USB2
MSC
AN1
11
27
0
0
Figure 18-10
OTG2
USB2
MSC
AN2
12
28
0
0
Freescale Semiconductor
Access: User read/write
BDLC GPT0 GPT1
13
29
0
0
0
and
14
30
0
0
0
15
31
0
0
0