MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 783

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Freescale Semiconductor
START_READW
CMD_RESUME Command Resume. Restores the SDHC_CMD_DAT_CONT register after READ/WAIT cycle for SDIO card.
STOP_READW
Address: Base + 0x0C
CMD_RESP_
BUS_WIDTH
LONG_OFF
Reset
Reset
Field
AIT
AIT
W
W
R
R
CMD_
RESU
ME
16
0
0
0
0
Figure 28-5. SDHC Command and Data Control (SDHC_CMD_DAT_CONT) Register
0 Issues command to card.
1 Does not issue command to card.
Command Response Long Off. Allows STATUS[13] END_CMD_RESP bit to be self-cleared when condition
to generate this bit disappears. This is used in the Read/Wait cycle. For SD/MMC operation, keep this bit at 0.
0 Bit not cleared when read.
1 Allows bit clearance.
Stop Read/Wait. Ends the Read/Wait cycle for SDIO. When this bit is set, SDHC does not drive DAT2 output
low so the SDIO card would end the Read/Wait cycle. For operation of SD/MMC, keep this bit at 0.
0 No effect.
1 Ends Read/Wait cycle.
Start Read/Wait. Starts the Read/Wait cycle for SDIO. When this bit is set, SDHC makes the DAT2 output low
and forces the SDIO card to enter READWAIT cycle. For SD/MMC operation, keep this bit at 0.
0 No effect.
1 Starts Read/Wait cycle.
Bus Width. Specifies the width of the data bus. These two bits must be set according to current card bit mode.
00 1-bit.
01 Reserved.
10 4-bit.
11 Reserved.
17
0
0
0
1
0
18
0
0
0
2
0
Table 28-7. SDHC_CMD_DAT_CONT field descriptions
RESP_
CMD_
LONG
_OFF
19
0
0
0
3
MPC5125 Microcontroller Reference Manual, Rev. 2
STOP_
READ
WAIT
20
4
0
0
0
START
DWAIT
_REA
21
0
0
0
5
BUS_WIDTH
22
0
0
0
6
23
0
0
0
7
Description
INIT
24
8
0
0
0
25
9
0
0
0
0
10
26
0
0
0
0
Secure Digital Host Controller (SDHC)
_READ
WRITE
11
27
0
0
0
DATA_
ENAB
LE
12
28
0
0
0
Access: User read/write
13
29
0
0
0
FORMAT_OF_
RESPONSE
14
30
0
0
0
28-11
15
31
0
0
0