MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 468

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Integrated Programmable Interrupt Controller (IPIC)
18-20
Address: Base + 0x24
RTC ALARM
Reset
Reset
RTC SEC
GPIO1
DMA2
PSC0
PSC1
PSC2
PSC3
GPT2
GPT3
GPT4
GPT5
GPT6
GPT7
W
W
Field
DDR
PMC
R
R RTC
SBA
DIU
ALAR
DIU
16
M
0
0
0
DMA
DDR
Figure 18-11. System Internal Interrupt Mask Low Register (IPIC_SIMSR_L)
17
2
0
0
1
PSC0 external interrupt source.
PSC1 external interrupt source.
PSC2 external interrupt source.
PSC3 external interrupt source.
GPT2 external interrupt source.
GPT3 external interrupt source.
GPT4 external interrupt source.
GPT5 external interrupt source.
GPT6 external interrupt source.
GPT7 external interrupt source.
DIU external interrupt source. Mask an interrupt by clearing the corresponding IPIC_SIMSRx bit. An
interrupt can be enabled by setting the corresponding IPIC_SIMSRx bit. The IPIC_SIMSRx can be read at
any time.
Note:
DMA2 external interrupt source.
GPIO1 external interrupt source.
RTC SEC external interrupt source.
RTC ALARM external interrupt source.
DDR external interrupt source.
SBA external interrupt source.
PMC external interrupt source.
• IPIC_SIMSRx bit positions are not changed according to their relative priority.
• Pending register bits that were set by multiple interrupt events can be cleared only by clearing all
• If an IPIC_SIMSRx bit is masked at the same time the corresponding IPIC_SIPNRx bit causes an
unmasked events in the corresponding event register.
interrupt request to the core, the error vector is issued (if no other interrupts pending). Therefore, always
include an error.
SBA
18
0
0
0
2
PMC
19
0
0
0
3
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 18-12. IPIC_SIMSR_L field descriptions
WKUP
PSC0 PSC1 PSC2 PSC3 GPT2 GPT3 GPT4 GPT5 GPT6 GPT7
USB2
OTG1
20
4
0
0
WKUP
OTG2
USB2
21
0
0
5
GPIO
22
0
2
0
6
TEMP
105C
23
0
0
7
Description
IIM
24
8
0
0
PRIO
MON
25
9
0
0
MSC
AN3
10
26
0
0
MSC
AN4
11
27
0
0
GPT1
12
28
0
2
0
Freescale Semiconductor
Access: User read/write
GPT1
13
29
0
3
0
GPT1
GPIO
14
30
1
0
4
0
GPT1
RTC
SEC
15
31
0
5
0