MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 310

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

DRAM Controller
it issues the active+precharge command for the bus one request. Because the DRAM controller sees it
cannot issue the read for the bus one request (the bank needs precharge + activate), it takes the bus two
request first. Because it can issue the read, the correct page is open. During this, it issues the
precharge + activate for the bus 1 request in the background. This request does not suffer from the bus two
request being serviced first.
The embedded priority manager determines the relative priority of each bus, and this is used by the DRAM
controller to determine which requests are more urgent.
11.2
11-2
•
Supports CAS latency of 2, 3, or 4 clock cycles.
SELF_REFRESH_REQ
SELF_REFRESH_ACK
Features
DDR Bus 0
DDR Bus 1
DDR Bus 2
DDR Bus 3
IPS BUS
Figure 11-1. Block Diagram of the Multi-port DRAM Controller
Command
Bypass
CONFIG
MPC5125 Microcontroller Reference Manual, Rev. 2
Read Block
Command
Interface
Engine
Buffers
DRAM
Write
DDR
Bus
All Config
DRAM_CKE
DRAM_CLK
DRAM_CLKB
DRAM_CS
DRAM_RAS
DRAM_CAS
DRAM_WE
DRAM_ODT
DRAM_ADDRESS[15:0]
DRAM_BA[2:0]
Write Block
Manager
Timing
INT_REQ
DDR
DDR_DQS_IN
DDR_DQ_IN
CONFIG
CONFIG
DDR_DQS_OUT
DDR_DM_OUT
DDR_DQ_OUT
DRAM_ODT
CONFIG
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