MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 191

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

6.4.7.7
This basic IFR transmitting flow can be interrupted for the same reasons as a normal message transmission.
The IFR transmit process can be adversely affected due to a loss of arbitration, an Invalid or Out of Range
Symbol, or due to a transmitter underrun caused by the CPU failing to service a TDRE interrupt in a timely
fashion. For a description of how these exceptions can affect the IFR transmit process, refer to
Section 6.4.5.2, “Transmitting Exceptions.”
6.4.8
Receiving an In-Frame Response with the BDLC module is similar to receiving a message frame. As each
byte of an IFR is received, the BDLC_DLCBSVR register indicates this to the CPU. An EOF indication
in the BDLC_DLCBSVR register indicates that the IFR (and message) is complete. Also, the IMSG bit
can also be used to command the BDLC module to mask any further network activity from the CPU,
including IFR bytes being received, until the next valid SOF is received.
6.4.8.1
Receiving an IFR from the SAE J1850 bus requires the same procedure that receiving a message does,
except that as each byte is received the Received IFR Byte (RxIFR) state is indicated in the
BDLC_DLCBSVR register. All other actions are the same. For an illustration of the steps described below,
refer to
Freescale Semiconductor
1. When RxIFR Interrupt occurs, retrieve IFR byte.
during the transmission of a Type 3 IFR the IFR control bits are cleared, the byte being transmitted
is discarded, and the BDLC_DLCBSVR register reflects the detected error.
If the Type 3 IFR being transmitted is made up of a single byte, the appropriate TMIFR bit and the
TEOD bit can be set at the same time. The BDLC module then treats that byte as the first and last
IFR byte to be sent.
When the first byte of an IFR following a valid EOD symbol is received that byte is placed in the
BDLC Data Register, and an RxIFR state is reflected in the BDLC_DLCBSVR register. No
indication of the EOD reception in made because the RxIFR state indicates that the main portion
of the message has ended and the IFR portion has begun.
Figure
Receiving An In-Frame Response (IFR)
Transmitting IFR Exceptions
Receiving an IFR with the BDLC Module
As with a message transmission, the IMSG bit should never be used to
ignore the BDLC module’s own IFR transmissions. This is again due to the
BDLC_DLCBSVR register bits being inhibited from updating until IMSG
is cleared, preventing the CPU from detecting any IFR-related state changes
that may be of interest.
6-25.
MPC5125 Microcontroller Reference Manual, Rev. 2
NOTE
Byte Data Link Controller (BDLC)
6-55