MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 442

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

IIM/Fusebox
17.3.2.5
Figure 17-5
17-6
Address: Base + 0x00C
PARITYE_M
Reset
Reset
SNSE_M
WPE_M
OPE_M
RPE_M
Field
W
W
R
R
16
0
0
0
0
0
shows the bits in the Fuse Control (IIM_FCTL) register.
Fuse Control (IIM_FCTL) Register
Write Protect Error Mask. Masks or unmasks IRQ generation due to WPE events.
0 WPE events do not cause an IRQ.
1 WPE events cause an IRQ.
Override Protect Error Mask. Masks or unmasks IRQ generation due to OPE events.
0 OPE events do not cause an IRQ.
1 OPE events cause an IRQ.
Read Protect Error Mask. Masks or unmasks IRQ generation due to RPE events.
0 RPE events do not cause an IRQ.
1 RPE events cause an IRQ.
Explicit Sense Cycle Error Mask. Masks or unmasks IRQ generation due to SNSE events.
0 SNSE events do not cause an IRQ.
1 SNSE events cause an IRQ.
Parity Error of Cache Mask. Masks or unmasks IRQ generation due to PARITYE events.
0 PARITYE events do not cause an IRQ.
1 PARITYE events cause an IRQ.
17
0
0
0
0
1
18
0
0
0
0
2
Figure 17-4. Error IRQ Mask Register (IIM_EMASK)
19
0
0
0
0
3
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 17-5. IIM_EMASK field descriptions
20
4
0
0
0
0
21
0
0
0
0
5
22
0
0
0
0
6
23
0
0
0
0
7
Description
24
8
0
0
0
0
WPE_
25
M
9
0
0
0
Table 17-6
OPE_
10
26
M
0
0
0
RPE_
11
27
M
0
0
0
Access: Supervisor read/write
describes the bit fields.
12
28
0
0
0
0
Freescale Semiconductor
SNSE
_M
13
29
0
0
0
PARIT
YE_M
14
30
0
0
0
15
31
0
0
0
0