MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 635

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

1
2
23.6.2
Freescale Semiconductor
0x0x3F3C–0x3FFF Reserved
(0xFF40_C000)
0x3900–0x3EFF
0x0000–0x38FF
FLASH_CMD1
Default absolute offset with IMMRBAR at default location of 0xFF40_0000. See
Map (XLBMEN + Mem Map).”
Reset value is indeterminate.
Offset from
NFC_BASE
(0x3F00)
Name
0x3F0C
0x3F1C
0x3F2C
0x3F00
0x3F04
0x3F08
0x3F10
0x3F14
0x3F18
0x3F20
0x3F24
0x3F28
0x3F30
0x3F34
0x3F38
Register Summary
1
W
W
R
R
SRAM buffer
Reserved
FLASH_CMD1—Flash Command 1 register
FLASH_CMD2—Flash Command 2 register
COL_ADDR—Column Address register
ROW_ADDR—Row Address register
FLASH_COMMAND_REPEAT—Flash Command Repeat
register
ROW_ADDR_INC—Row Address Increment register
FLASH_STATUS1—Flash Status 1 register
FLASH_STATUS2—Flash Status 2 register
DMA1_ADDR—DMA1 Address register
DMA_CONFIG—DMA Configuration register
CACHE_SWAP—Cache Swap register
SECTOR_SIZE—Sector Size register
FLASH_CONFIG—Flash Configuration register
DMA2_ADDR—DMA2 Address register
IRQ_STATUS—IRQ and Status register
16
0
17
1
FLASH_CMD_BYTE2
MPC5125 Microcontroller Reference Manual, Rev. 2
18
2
Table 23-3. NFC Register Summary
19
3
Table 23-2. NFC memory map
Register
20
4
21
5
22
6
23
7
24
8
25
Chapter 2, “System Configuration and Memory
9
Access
10
26
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FLASH_CMD_BYTE3
R
R
11
27
0x0FFE_0FFE
0x30FE_0000
0x007E_E001
0x000E_A631
0x0000_0000
0x1100_0000
0x0000_0000
0x0000_0001
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0420
0x0000_0000
0x0400_0000
Reset Value
NAND Flash Controller (NFC)
12
28
—
2
13
29
Section/Page
23.7.10/23-13
23.7.11/23-14
23.7.12/23-15
23.7.13/23-15
23.7.14/23-17
23.7.15/23-18
23.7.4/23-10
23.7.5/23-11
23.7.6/23-11
23.7.7/23-12
23.7.8/23-12
23.7.9/23-13
23.7.1/23-8
23.7.2/23-8
23.7.3/23-9
23.5/23-3
14
30
15
31
23-5