MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 696

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Programmable Serial Controller (PSC)
25.4.1.9
The ACR register controls Tx/Rx handshaking.
25-18
Address: Base + 0x1C
D_DCD
D_CTS
Reset
Field
Field
DCD
IEC1
IEC0
CTS
W
R
Auxiliary Control Register (ACR)
Delta DCD.
0 No change-of-state has occurred since the last time the CPU read the IPCR. A read of the IPCR also clears
1 A change of state (1/16 or 1bit duration determined by the CSR, CTUR and CTLR) has occurred at DCD
Delta CTS.
0 No change-of-state has occurred since the last time the CPU read the IPCR. A read of the IPCR also clears
1 A change of state, lasting a certain time, has occurred at CTS input. When this bit is set, the ACR can be
After the enable of the PSC, the CPU must read this bit to make sure this bit is cleared at the beginning of the
transmission.
Current state of DCD port. This input is double latched.
0 The current state of the DCD input port is low.
1 The current state of the DCD input port is high.
Current state of CTS port. This input is double latched.
0 The current state of the CTS input port is low.
1 The current state of the CTS input port is high.
Interrupt Enable Control for D_DCD.
0 D_DCD has no effect on the IPC in the ISR.
1 When the D_DCD becomes high, IPC bit in the ISR sets (causing an interrupt if mask is set).
Interrupt Enable Control for D_CTS.
0 D_CTS has no effect on the IPC in the ISR.
1 When the D_CTS becomes high, IPC bit in the ISR sets (causing an interrupt if mask is set).
After enabling the PSC, the D_CTS bit can be set. Therefore, it’s important to clear the D_CTS bit before
enabling this interrupt.
0
0
0
the IPCR D_DCD bit.
input. When this bit is set, the ACR can be programmed to generate an interrupt to the processor.
the IPCR D_CTS bit.
programmed to generate an interrupt to the processor.
Figure 25-21. Auxiliary Control Register for all Modes (ACR)
1
0
0
Table 25-13. IPCR field descriptions (continued)
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 25-14. ACR field descriptions
0
0
2
0
0
3
Description
Description
0
0
4
0
0
5
Freescale Semiconductor
Access: User read/write
0
0
6
0
0
7