MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 170

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Byte Data Link Controller (BDLC)
6.4.3.1
The Receiver section of the BDLC module includes a digital low pass filter to remove narrow noise pulses
from the incoming message. An outline of the digital filter is shown in
J1850_RX Pad
6.4.3.2
The clock for the digital filter is provided by the MUX Interface clock. At each positive edge of the clock
signal, the current state of the Receiver input signal from the J1850_RX pad is sampled. The J1850_RX
signal state is used to determine whether the counter should increment or decrement at the next positive
edge of the clock signal.
The counter increments if the input data sample is high but decrement if the input sample is low. The
counter then progresses up towards 15 if, on average, the J1850_RX signal remains high or progress down
towards 0 if, on average, the J1850_RX signal remains low.
When the counter eventually reaches the value 15, the digital filter decides that the condition of the
J1850_RX signal is at a stable logic level one and the Data Latch is set, causing the Filtered Rx Data signal
to become a logic level one. Furthermore, the counter is prevented from overflowing and can only be
decremented from this state.
Alternatively, should the counter eventually reach the value 0, the digital filter decides that the condition
of the J1850_RX signal is at a stable logic level zero and the Data Latch is reset, causing the Filtered Rx
Data signal to become a logic level zero. Furthermore, the counter is prevented from underflowing and can
only be incremented from this state.
The Data Latch retains its value until the counter next reaches the opposite end point, signifying a definite
transition of the J1850_RX signal.
6.4.3.3
The performance of the digital filter is best described in the time domain rather than the frequency domain.
If the signal on the J1850_RX signal transitions, there is a delay before that transition appears at the
Filtered Rx Data output signal. This delay is between 15 and 16 clock periods, depending on where the
6-34
Rx Data
MUX Interface
From
Clock
MUX Interface—Rx Digital Filter
Operation
Performance
Input Sync
d
q
Figure 6-18. BDLC Module Rx Digital Filter Block Diagram
MPC5125 Microcontroller Reference Manual, Rev. 2
up/down
4-Bit Up/Down Counter
out
4
Comparator
Figure
Count
Edge
and
6-18.
Freescale Semiconductor
d
q
Filtered
Rx Data
Out