MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 45

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

2.2.5.1.6
Figure 2-5
2.2.5.1.7
Figure 2-6
Freescale Semiconductor
Address: Base + 0x00A4
Address: Base + 0x00C4
Reset
Reset
Reset
Reset
Field
SIZE
W
W
W
W
R
R
R
R
16
16
0
0
0
0
0
0
0
shows the DDR Local Access Window Attributes Register (DDRLAWAR).
0
shows the SRAM Base Address Register (SRAMBAR).
0
DDR Local Access Window Attributes Register (DDRLAWAR)
SRAM Base Address Register (SRAMBAR)
Identifies the size of the window from the starting address. Window size is 2
000000–011000 Reserved. Window is undefined.
011001
011010
011011
.............
. . . . . . .
.............
011110
011111–111111 Reserved. Window is undefined.
17
17
Figure 2-5. DDR Local Access Window Attributes Register (DDRLAWAR)
0
0
0
0
0
0
0
1
1
18
18
0
0
0
0
1
0
0
2
2
Figure 2-6. SRAM Base Address Register (SRAMBAR)
19
19
0
0
0
0
1
0
0
3
3
MPC5125 Microcontroller Reference Manual, Rev. 2
64 MB
128 MB
256 MB
2
2 GB
(SIZE + 1)
Table 2-9. DDRLAWAR field descriptions
20
20
4
0
0
0
0
4
0
0
0
bytes
21
21
0
0
0
0
0
0
0
5
5
BASE_ADDR
22
22
0
0
0
0
0
0
0
6
6
23
23
0
0
0
0
0
0
0
7
7
Description
System Configuration and Memory Map (XLBMEN + Mem Map)
24
24
8
0
0
0
0
8
0
0
0
25
25
9
0
0
0
0
9
0
0
0
10
26
10
26
0
0
0
0
0
0
11
27
11
27
0
0
1
0
0
0
(SIZE+1)
12
28
12
28
0
0
1
0
0
0
bytes.
Access: User read/write
SIZE
Access: User read/write
13
29
13
29
0
0
0
0
0
0
14
30
14
30
0
0
0
0
0
0
0
15
31
15
31
2-11
0
0
1
0
0
0
0