MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 676

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Power Management Control Module (PMC)
In this mode, bus snooping is disabled. The core waits unit the snoop bus is idle before entering core PLL
change mode.
After the core enters sleep mode, PMC provides the updated core PLL configuration to the core.
During the core PLL change process, the PMC blocks all interrupts to the core to make sure it is not
awakened while the PLL is not locked. The wakeup time is listed in
the PMC unblocks the interrupts and the PMC interrupt (PMC_PMCER[INT2], see
“PMC Event Register
24.3.7
This mode can change the system clock divide ratio (SYS_DIV), also referred to as pre-divider ratio
(PRE_DIV). To change the system clock divide ratio, write the new SYS_DIV value to the shadow register
(SCFR2) in the CLOCK module, and then set the PREDIV bit in the PMC_PMCCR register. Because the
core PLL needs relock, the core must enter sleep mode. To enter sleep mode, the POW bit in the e300 MSR
register must be set, then set the sleep bit (HID0[10] = 1).
In case DDR1 or DDR2 DRAM is used, the DRAM PLL needs to relock because DRAM clock frequency
changes. The user can set the PMC_PMCCR[DDROFF] bit so that DRAM goes to self-refresh
automatically. It is required that the DRAM controller is configured for putting the DRAM in self-refresh
state upon receipt of the request from PMC.
In this mode, bus snooping is disabled. The core waits unit the snoop bus is idle before entering Core PLL
change mode.
After the core enters sleep mode, PMC waits several processor clocks for the core PLL to be switched off,
and then asserts a copy_shadow signal to enable the CLOCK module to copy the new SYS_DIV value and
update system clock frequency.
During the PRE_DIV copy enable process (i.e. from the point when the e300 core initiates sleep mode
entry to when the core PLL is locked to the new system clock input), PMC blocks all interrupts to the core
to make sure it’s not waked up while the PLL is not locked. The wakeup time is listed in
the wakeup time, the PMC releases the interrupts and the PMC interrupt (PMC_PMCER[INT2], see
Section 24.2.2.2, “PMC Event Register
mode. Then, the system clock divide ratio change is done.
24.3.8
Table 24-10
low-power mode, core PLL change mode, or pre-divider copy mode.
24-12
PRE_DIV Copy Enable Mode
Low-Power Configurations
summarizes the valid PMC and e300 settings that can be used to put the module into
Changing pre-divider factor changes all on-chip frequencies. This may
upset certain peripherals, and require re-initialization. The device drivers of
these peripherals must take care of this.
(PMC_PMCER)”) can be used to wakeup the core from sleep mode.
MPC5125 Microcontroller Reference Manual, Rev. 2
(PMC_PMCER)”) can be used to wakeup the core from sleep
NOTE
Table
24-8. After the wakeup time,
Freescale Semiconductor
Section 24.2.2.2,
Table
24-8. After