MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 933

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

When the pre-operations are complete and pre-conditions are met, the host controller sets the Reclamation
bit in the USB_USBSTS register to a one and then begins executing one or more transactions using the
endpoint information in the queue head. The host controller iterates qHTransactionCounter times in this
state executing transactions. After each transaction is executed, qHTransactionCounter is decremented by
one. The host controller exits this state when one of the following events occurs:
The results of each transaction is recorded in the on-chip overlay area. If data was successfully moved
during the transaction, the transfer state in the overlay area is advanced. To advance the queue head’s
transfer state, the Total Bytes to Transfer field is decremented by the number of bytes moved in the
Freescale Semiconductor
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an S-mask value of 00100000b would evaluate to true only when USB_FRINDEX[2:0] is equal to
101b. If this condition is met then the host controller considers this queue head for a transaction.
Asynchronous Transfer Pre-operations and Pre-condition Criteria
If the queue head is not for an interrupt endpoint (a zero S-mask field), then the host controller
performs one pre-operation and then evaluates one pre-condition criteria: The pre-operation is:
— Checks the Nak counter reload state. It may be necessary for the host controller to reload the
The pre-condition evaluated is:
— Whether or not the NakCnt field has been reloaded, the host controller checks the value of the
Transfer Type Independent Pre-operations
Regardless of the transfer type, the host controller always performs at least one pre-operation and
evaluates one pre-condition. The pre-operation is:
— A host controller internal transaction (down) counter qHTransactionCounter is loaded from the
The pre-conditions evaluated are:
— The host controller determines whether there is enough time in the micro-frame to complete
— If the value of qHTransactionCounter for an interrupt endpoint is zero, then the host controller
The qHTransactionCounter decrements to zero, or
The endpoint responds to the transaction with any handshake other than an ACK
The transaction experiences a transaction error, or
The Active bit in the queue head goes to a zero, or
There is not enough time in the micro-frame left to execute the next transaction.
Nak Counter field. The reload is performed at this time.
NakCnt field in the queue head. If NakCnt is non-zero, or if the Reload Nak Counter field is
zero, then the host controller considers this queue head for a transaction.
queue head’s Mult field. A host controller implementation is allowed to ignore this for queue
heads on the asynchronous list. It is mandatory for interrupt queue heads. Software should
ensure that the Mult field is set appropriately for the transfer type.
this transaction. If there is not enough time to complete the transaction, the host controller exits
this state.
exits this state.
For a high-bandwidth interrupt OUT endpoint, the host controller may
optionally immediately retry the transaction if it fails.
MPC5125 Microcontroller Reference Manual, Rev. 2
NOTE
Universal Serial Bus Interface with On-The-Go
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or
32-105