MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 708

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Programmable Serial Controller (PSC)
25-30
SIM[3:0]
SyncPol
GenClk
SHDIR
ClkPol
Field
ESAI
I2S
Codec. Shift Direction.
0 MSB first.
1 LSB first.
Other Modes. Reserved.
PSC operation mode.
CAUTION: When the operating mode change occurs, all Rx/Tx and error statuses are reset. Rx and Tx are
disabled.
Codec. Generate Bit Clock and FrameSync. Not used to enable the SPI master mode, but this bit must also
be set to the MSTR to enable the SPI master mode.
0 Use bit clock and FrameSync provided by external device.
1 Use bit clock and FrameSync generated internally from MCLK.
Other Modes. Reserved.
Codec. I2S mode
0 No I2S mode supported.
1 PSC works in I2S mode.
Other Modes. Reserved.
Codec. Bit Clock Polarity
0 Data in is sampled on the falling edge of the BCLK and data out is shifted on the rising edge.
1 Data in is sampled on the rising edge of the BCLK and data out is shifted on the falling edge.
Other Modes. Reserved.
Note: This bit must be cleared during SPI mode.
Codec. FrameSync Polarity, must be cleared during SPI mode
0 FrameSync is low true.
1 FrameSync is high true.
Codec I2S. FrameSync Polarity.
0 Frame starts if LRCK is low.
1 Frame starts if LRCK is high.
Other Modes. Reserved.
Codec. Enhanced Serial Audio Interface
0 PSC does not support the ESAI mode.
1 PSC supports the ESAI mode. This mode allows the PSC to send and receive more the one data word per
Other Modes. Reserved.
frame, if the frame length is greater than the word length. The PSC send only complete data words.
0000 = UART mode, DCD input ignored.
1000 = UART mode, DCD input is effective.
0001 = Codec mode, 8-bit data.
1001 = Codec mode, 12-bit data.
0010 = Codec mode, 16-bit data.
1010 = Codec mode, 20-bit data.
x011 = AC97 mode.
0100 = Reserved.
1100 = Reserved.
x101 = Reserved.
x110 = Reserved.
0111 = Codec mode, 24-bit data.
1111 = Codec mode, 32-bit data.
Table 25-26. SICR field descriptions (continued)
MPC5125 Microcontroller Reference Manual, Rev. 2
Description
Freescale Semiconductor