MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 939

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

The only valid adjustment the host controller may make to C_Page is to increment by one.
32.6.9.7
The link path(s) from the periodic frame list to a queue head establishes in which frames a transaction can
be executed for the queue head. Queue heads are linked into the periodic schedule so they are polled at the
appropriate rate. System software sets a bit in a queue head's S-Mask to indicate which micro-frame within
a one millisecond period a transaction should be executed for the queue head. Software must ensure all
queue heads in the periodic schedule have S-Mask set to a non-zero value. An S-mask with a zero value
in the context of the periodic schedule yields undefined results.
If the desired poll rate is greater than one frame, system software can use a combination of queue head
linking and S-Mask values to spread interrupts of equal poll rates through the schedule so that the periodic
bandwidth is allocated and managed in the most efficient manner possible. Some examples are illustrated
in
32.6.9.8
The host controller sets an interrupt to be signaled at the next interrupt threshold when the completed
transfer (qTD) has an interrupt on complete (IOC) bit set, or when a transfer (qTD) completes with a short
packet. If system software needs multiple qTDs to complete a client request (like a control transfer) the
intermediate qTDs do not require interrupts. System software may only need a single interrupt to notify it
that the complete buffer has been transferred. System software may set IOCs to occur more frequently. A
motivation for this may be that it wants early notification so interface data structures can be re-used in a
timely manner.
Freescale Semiconductor
0, 2, 4, 6, 8,....
S-Mask = 0x01
0, 2, 4, 6, 8,...
S-Mask = 0x02
Table
Reference
Sequence
•
•
•
Frame
The current transaction does not span a page boundary. The value of C_Page is not adjusted by the
host controller.
The current transaction does span a page boundary. The host controller must detect the page cross
condition and advance to the next buffer while streaming data to/from the USB.
The current transaction completes on a page boundary (the last byte moved for the current
transaction is the last byte in the page for the current page pointer). The host controller must
increment C_Page before writing back status for the transaction.
32-74.
Adding Interrupt Queue Heads to the Periodic Schedule
Managing Transfer Complete Interrupts from Queue Heads
A queue head for the bInterval of two milliseconds (16 micro-frames) is linked into the periodic schedule so
it is reachable from the periodic frame list locations indicated in the previous column. In addition, the S-Mask
field in the queue head is set to 0x01, indicating that the transaction for the endpoint should be executed on
the bus during micro-frame 0 of the frame.
Another example of a queue head with a bInterval of two milliseconds is linked into the periodic frame list at
exactly the same interval as the previous example. However, the S-Mask is set to 0x02 indicating that the
transaction for the endpoint should be executed on the bus during micro-frame 1 of the frame.
Table 32-74. Example Periodic Reference Patterns for Interrupt Transfers
MPC5125 Microcontroller Reference Manual, Rev. 2
Description
Universal Serial Bus Interface with On-The-Go
32-111