MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 868

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Universal Serial Bus Interface with On-The-Go
32-40
SUSP
Field
FPR
PR
Port Reset.
In host mode, when software writes a 1 to this bit, the bus-reset sequence as defined in the USB specification
revision 2.0 is started. This bit automatically changes to 0 after the reset sequence is complete. This behavior
is different from EHCI where the host controller driver is required to set this bit to 0 after the reset duration is
timed in the driver.
For the DR module in device mode, this bit is a read-only status bit. Device reset from the USB bus is also
indicated in the USB_USBSTS register.
0 Port is not in Reset.
1 Port is in Reset.
This field is 0 if Port Power (PP) is 0.
Suspend
In host mode:
The port enabled bit (PE) and suspend (SUSP) bit define the port states as follows:
0x Disable.
10 Enable.
11 Suspend.
When in suspend state, downstream propagation of data is blocked on this port, except for port reset. The
blocking occurs at the end of the current transaction if a transaction was in progress when this bit was written
to 1. In the suspend state, the port is sensitive to resume detection. Bit status does not change until the port
is suspended and there may be a delay in suspending a port if there is a transaction currently in progress on
the USB.
The module unconditionally sets this bit to 0 when software sets the Force Port Resume (FPR) bit to 0. The
host controller ignores a write of 0 to this bit. If host software sets this bit to 1when the port is not enabled (the
PE bit is 0), results are undefined.
This field is 0 if Port Power (PP) is 0 in host mode.
For the OTG module in device mode:
0 Port not in suspend state. Default.
1 Port in suspend state.
In device mode, this bit is a read-only status bit.
Force Port Resume. This bit is not-EHCI compatible.
0 No resume (K-state) detected/driven on port.
1 Resume detected/driven on port.
In Host mode:
Software sets this bit to one to drive resume signaling. The controller sets this bit to one if a J-to-K transition
is detected while the port is in the suspend state. When this bit transitions to 1, a J-to-K transition is detected,
and the port change detect bit in the USB_USBSTS register is also set to one. This bit automatically changes
to 0 after the resume sequence is complete. This behavior is different from EHCI where the host controller
driver is required to set this bit to 0 after the resume duration is timed in the driver.
When the controller owns the port, the resume sequence follows the defined sequence documented in the
USB Specification Revision 2.0. The resume signaling (full-speed K) is driven on the port as long as this bit is
set. This bit remains set until the port has switched to the high-speed idle. Writing a zero has no effect because
the port controller times the resume operation to clear the bit the port control state switches to HS or FS idle.
This field is 0 if Port Power (PP) is 0 in host mode.
In Device mode:
After the device has been in suspend state for 5 msec or more, software must set this bit to one to drive
resume signaling before clearing. the OTG controller sets this bit to one if a J-to-K transition is detected while
the port is in the suspend state. The bit is cleared when the device returns to normal operation. Also, when
this bit transitions to a one because a J-to-K transition is detected, the port change detect bit in the
USB_USBSTS register is also set to one.
Table 32-32. USB_PORTSCn field descriptions (continued)
MPC5125 Microcontroller Reference Manual, Rev. 2
Description
Freescale Semiconductor