MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 248

IC MCU 32BIT E300 324TEPBGA

MPC5125YVN400

Manufacturer Part Number
MPC5125YVN400
Description
IC MCU 32BIT E300 324TEPBGA
Manufacturer
Freescale Semiconductor
Series
MPC51xxr

Specifications of MPC5125YVN400

Core Processor
e300
Core Size
32-Bit
Speed
400MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, USB OTG
Peripherals
DMA, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.33 V ~ 1.47 V
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
324-PBGA
Processor Series
MPC51xx
Core
e300
Data Bus Width
32 bit
Development Tools By Supplier
TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
Maximum Clock Frequency
400 MHz
Operating Supply Voltage
1.4 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Data Ram Size
32 KB
I/o Voltage
3.3 V
Interface Type
CAN, I2C
Minimum Operating Temperature
- 40 C
Program Memory Size
32 bit
Cpu Speed
400MHz
Embedded Interface Type
CAN, I2C, SPI, UART, USB
Digital Ic Case Style
TEPBGA
No. Of Pins
324
Rohs Compliant
Yes
Cpu Family
MPC5xx
Device Core Size
32b
Frequency (max)
400MHz
Total Internal Ram Size
32KB
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
324
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MPC5125YVN400
Manufacturer:
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Quantity:
135
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MPC5125YVN400
Manufacturer:
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Part Number:
MPC5125YVN400
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Direct Memory Access (DMA)
Figure 9-24
Figure 9-25
9-28
Address: Base + 0x1000 + (32 × n) + 0x0008
NBYTES[31:0] Inner Minor Byte Transfer Count. Number of bytes to be transferred in each service request of the channel.
SOFF[15:0]
DMOD[4:0]
SSIZE[2:0]
DSIZE[2:0]
Reset
Reset
Field
Field
W
W
R
R
See
16
0
and
and
Table 9-1
Source data transfer size
000 8-bit
001 16-bit
010 32-bit
011 Reserved
100 16-byte
101 32-byte
110 Reserved
111 Reserved
The attempted specification of a reserved source size produces a configuration error.
Destination address modulo. See the SMOD[5:0] definition.
Destination data transfer size. See the SSIZE[2:0] definition.
Source address signed offset. Sign-extended offset applied to the current source address to form the
next-state value as each source read is completed.
As a channel is activated, the contents of the appropriate TCD is loaded into the DMA_ENGINE, and the
appropriate reads and writes perform until the complete byte transfer count has been transferred. This is an
indivisible operation and cannot be stalled or halted. After the minor count is exhausted, the current values of
the SADDR and DADDR are written back into the local memory, the major iteration count is decremented and
restored to the local memory. If the major iteration count is completed, additional processing is performed.
The NBYTES value of 0x0000_0000 is interpreted as 0x1_0000_0000, thus specifying a 4 GB transfer.
Table 9-24
Table 9-25
17
1
and
18
2
Table
Table 9-23. TCDn Word 1 field descriptions (continued)
define word 2 of the TCDn structure, the NBYTES field.
define word 3 of the TCDn structure, the SLAST field.
19
Figure 9-24. TCDn Word 2 (TCDn.NBYTES) Field
3
9-21.
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 9-24. TCDn Word 2 field descriptions
20
4
21
5
22
6
NBYTES[31:16]
NBYTES[15:00]
23
7
Description
Description
24
8
25
9
10
26
11
27
12
28
Freescale Semiconductor
Access: User read/write
13
29
14
30
15
31

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