MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 959

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

time-frame references for both the B-Frames (HS/FS/LS Bus) and the H-Frames. At the bottom is
illustrated the relationship between the scope of an siTD description and the time references. Each
H-Frame corresponds to a single location in the periodic frame list. The implication is that each siTD is
reachable from a single periodic frame list location at a time.
Each case is described below:
Software must apply the following rules when calculating the schedule and linking the schedule data
structures into the periodic schedule:
Freescale Semiconductor
•
•
•
•
H-Frame
4
5
Case 1: One siTD is sufficient to describe and complete the isochronous split transaction because
the whole isochronous split transaction is tightly contained within a single H-Frame.
Case 2a, 2b: Although both INs and OUTs can have these footprints, OUTs always take only one
siTD to schedule. However, INs (for these boundary cases) require two siTDs to complete the
scheduling of the isochronous split transaction. The siTDX is used to always issue the start-split
and the first N complete-splits. The full-speed transaction (for these cases) can deliver data on the
full-speed bus segment during micro-frame 7 of H-Frame
The complete splits are scheduled using siTD
data must use the buffer pointer from siTD
siTD
Software must ensure that an isochronous split-transaction is started so it completes before the end
of the B-Frame.
Software must ensure that for a single full-speed isochronous endpoint, there is never a start-split
and complete-split in H-Frame, micro-frame 1. This is mandated as a rule so that case 2a and case
2b can be discriminated. According to the core USB specification, the long isochronous transaction
illustrated in Case 2b could be scheduled so the start-split was in micro-frame 1 of H-Frame N and
the last complete-split would need to occur in micro-frame 1 of H-Frame N+1. However, it is
B-Frame
5
6
Y–1
X+1
6
7
Y–1
from H-Frame
7
0
0
1
Case 1
1
2
Figure 32-69. siTD Scheduling Boundary Examples
MPC5125 Microcontroller Reference Manual, Rev. 2
H-Frame
2
Y+2
3
siTD
B-Frame
4
3
is to use siTD
X
Y
Full-Speed Transaction
4
5
Y
Case 2a
5
6
Back Pointer
6
7
X+2
X+1
7
0
's back pointer.
X+2
. The only way for the host controller to reach
0
1
(not shown). The complete-splits to extract this
1
2
H-Frame
2
siTD
3
B-Frame
Y+1
Case 2b
4
X+1
3
Universal Serial Bus Interface with On-The-Go
, or micro-frame 0 of H-Frame
Y+1
4
5
Y+1
5
6
6
7
7
0
H-Frame
0
1
B-Frame
1
2
Y+2
2
3
Y+2
32-131
Y+2
.