MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 401

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

ETH_IADDR1 and ETH_IADDR2 registers. In the case of an individual hash match, AR_HM_B is set to
0. Again, the receiver accepts or rejects the frame based on pause frame detection, shown in
ar_hm_b and ar_em_b are set to 1. In this case, if promiscuous mode is enabled (r_cntrl.prom = 1), the
frame is accepted and the MISS bit in the receive buffer descriptor is set. Otherwise, the frame is rejected
and the MISS bit is cleared.
Similarly, if the DA is a broadcast address, broadcast reject (ETH_R_CNTRL[BC_REJ]) is asserted, and
promiscuous mode is enabled, the frame is accepted, and the MISS bit in the receive buffer descriptor is
set. Otherwise, the frame is rejected and the MISS bit is cleared.
In general, when a frame is rejected, it is flushed from the FIFO.
Freescale Semiconductor
If neither a hash match (group or individual), nor an exact match (group or individual) occur, then both
NOTES:
PROM — field in ETH_R_CNTRL register (PROMiscous mode)
Pause Frame — valid PAUSE frame received
BC_REJ — field in ETH_R_CNTRL register (BroadCast REJect)
Set BC bit in Receive BD
Receive Frame
Figure 14-30. Ethernet Address Recognition — Receive Block Decisions
False
MPC5125 Microcontroller Reference Manual, Rev. 2
BC_REJ = 1
Flush from FIFO
Reject Frame
?
True
True
False
Broadcast Addr
Accept/Reject
PROM = 1
Set BC bit in Receive BD if broadcast
Set MC bit in Receive BD if multicast
Frame
?
?
Set M (Miss) bit in Receive BD
Receive Frame
True
False
False
False
Recognition
Hash Match
Exact Match
Receive
Address
?
?
Set MC bit in Receive BD if multicast
True
True
Receive Frame
Receive Frame
False
Pause Frame
?
Fast Ethernet Controller (FEC)
Flush from FIFO
Reject Frame
True
Figure
14-30.
14-45