MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 482

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Integrated Programmable Interrupt Controller (IPIC)
18.2.1.22 System Management Interrupt Vector Register (IPIC_SMVCR)
The System Management Interrupt Vector Register (IPIC_SMVCR), shown in
7-bit code
highest priority level.
18-34
Address: Base + 0x60
Address: Base + 0x64
Reset
Reset
Reset
Reset
CVEC
Field
W
W
W
W
R
R
R
R
16
(Table
16
0
0
0
0
0
0
0
0
0
0
Critical interrupt vector. Specifies a 7-bit unique number of the IPIC’s highest priority critical interrupt source,
pending to the core. When a critical interrupt request occurs, IPIC_SCVCR can be read. If there are multiple
critical interrupt sources, IPIC_SCVCR latches the highest priority critical interrupt. The CVEC field correctly
reflects all of the interrupt vectors (See
The value of SCVEC cannot change while it is being read.
Note: While the upper 24 bits of this register are set to zero at the release of PORESET, they can and will
Figure 18-26. System Management Interrupt Vector Register (IPIC_SMVCR)
17
17
0
0
0
0
0
0
0
0
1
1
18-27) representing the unmasked system management interrupt (SMI) source of the
Figure 18-25. System Critical Interrupt Vector Register (IPIC_SCVCR)
change during device operation. Therefore, when using the value of the CVEC field, be sure to mask
off the upper 24 bits of this register.
18
18
0
0
0
0
0
0
0
0
2
2
19
19
0
0
0
0
0
0
0
0
3
3
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 18-26. IPIC_SCVCR field descriptions
20
20
4
0
0
0
0
4
0
0
0
0
21
21
0
0
0
0
0
0
0
0
5
5
22
22
0
0
0
0
0
0
0
0
6
6
Table 18-4
23
23
0
0
0
0
0
0
0
0
7
7
Description
for details).
24
24
8
0
0
0
0
8
0
0
0
0
25
25
9
0
0
0
9
0
0
0
10
26
10
26
0
0
0
0
0
0
11
27
11
27
0
0
0
0
0
0
Figure
MVEC
CVEC
12
28
12
28
0
0
0
0
0
0
Freescale Semiconductor
Access: User read/write
Access: User read/write
18-26, contains a
13
29
13
29
0
0
0
0
0
0
14
30
14
30
0
0
0
0
0
0
15
31
15
31
0
0
0
0
0
0