MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 399

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

14.6.1.1
The FEC fetches transmit buffer descriptors (TxBDs) and the corresponding transmit data continuously
until the transmit FIFO is full. It does not determine whether the TxBD to be fetched is already being
processed internally (as a result of a wrap). As the FEC nears the end of the transmission of one frame, it
begins to DMA the data for the next frame. To remain one BD ahead of the DMA, it also fetches the TxBD
for the next frame. It is possible that the FEC fetches from memory a BD that has already been processed
but not yet written back (it is read a second time with the R bit remains set). In this case, the data is fetched
and transmitted again.
Using at least three TxBDs fixes this problem for large frames, but not for small frames. To ensure correct
operation for large or small frames, one of the following must be true:
14.6.2
The FEC receiver is designed to work with almost no intervention from the host and can perform address
recognition, CRC checking, short frame checking, and maximum frame length checking.
When the driver enables the FEC receiver by asserting ETHER_EN, it immediately starts processing
receive frames. When RX_DV asserts, the receiver checks for a valid PA/SFD header. If the PA/SFD is
valid, it is stripped and the frame is processed by the receiver. If a valid PA/SFD is not found, the frame is
ignored.
In serial mode, the first 16 bit times of RX_D0 following assertion of RX_DV (RENA) are ignored.
Following the first 16 bit times, the data sequence is checked for alternating 1/0s. If a 11 or 00 data
sequence is detected during bit times 17 to 21, the remainder of the frame is ignored. After bit time 21, the
data sequence is monitored for a valid SFD (11). If a 00 is detected, the frame is rejected. When a 11 is
detected, the PA/SFD sequence is complete.
In MII mode, the receiver checks for at least one byte matching the SFD. Zero or more PA bytes may occur,
but if a 00 bit sequence is detected prior to the SFD byte, the frame is ignored.
After the first six bytes of the frame have been received, the FEC performs address recognition on the
frame.
After a collision window (64 bytes) of data has been received, and if address recognition has not rejected
the frame, the receive FIFO is signalled that the frame has been accepted and may be passed on to the
Freescale Semiconductor
•
•
•
The FEC software driver ensures that there is always at least one TxBD with the ready bit cleared.
Every frame uses more than one TxBD and every TxBD but the last is written back immediately
after the data is fetched.
The FEC software driver ensures a minimum frame size, n. The minimum number of TxBDs is
then (Tx FIFO Size ÷ (n + 4)) rounded up to the nearest integer (though the result cannot be less
than three). The default Tx FIFO size is 192 bytes; this size is programmable.
FEC Frame Reception
Duplicate Frame Transmission
The FEC receive block transfers blocks of 16 bytes to the receive buffer
even if the message length is not divisible by 16 bytes. Therefore, if the
message length is not divisible by 16 bytes, extra bytes are added.
MPC5125 Microcontroller Reference Manual, Rev. 2
NOTE
Fast Ethernet Controller (FEC)
14-43