HD64F3437STF16V Renesas Electronics America, HD64F3437STF16V Datasheet - Page 103

• Manufacturer Part Number: HD64F3437STF16V
• Description: MCU 3/5V 60K PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300r

Specifications of HD64F3437STF16V

• Core Processor: H8/300
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: Host Interface, I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Bits 7 to 0—IRQ
IRQ
Bits 7 to 0:
IRQ7SC to IRQ0SC
0
1
IRQ Enable Register (IER)
Bits 7 to 0—IRQ7 to IRQ0 Enable (IRQ7E to IRQ0E): These bits enable or disable the IRQ
IRQ
Bits 7 to 0:
IRQ7E to IRQ0E
0
1
When edge sensing is selected (by setting bits IRQ7SC to IRQ0SC to 1), it is possible for an
interrupt-handling routine to be executed even though the corresponding enable bit (IRQ7E to
IRQ0E) is cleared to 0 and the interrupt is disabled. If an interrupt is requested while the enable bit
(IRQ7E to IRQ0E) is set to 1, the request will be held pending until served. If the enable bit is
cleared to 0 while the request is still pending, the request will remain pending, although new
requests will not be recognized. If the interrupt mask bit (I) in the CCR is cleared to 0, the
interrupt-handling routine can be executed even though the enable bit is now 0.
If execution of interrupt-handling routines under these conditions is not desired, it can be avoided
by using the following procedure to disable and clear interrupt requests.
1. Set the I bit to 1 in the CCR, masking interrupts. Note that the I bit is set to 1 automatically
2. Clear the desired bits from IRQ7E to IRQ0E to 0 to disable new interrupt requests.
3. Clear the corresponding IRQ7SC to IRQ0SC bits to 0, then set them to 1 again. Pending IRQn
Bit
Initial value
R/W
when execution jumps to an interrupt vector.
interrupt requests are cleared when I = 1 in the CCR, IRQnSC = 0, and IRQnE = 0.
7
0
to IRQ
interrupts individually.
0
are level-sensed or sensed on the falling edge.
7
IRQ7E
to IRQ
R/W
7
0
Description
An interrupt is generated when IRQ
An interrupt is generated by the falling edge of the IRQ
Description
IRQ
IRQ
0
Sense Control (IRQ7SC to IRQ0SC): These bits determine whether
IRQ6E
7
7
R/W
to IRQ
to IRQ
6
0
0
0
interrupt requests are disabled.
interrupt requests are enabled.
IRQ5E
R/W
5
0
IRQ4E
R/W
4
0
IRQ3E
7
R/W
to IRQ
3
0
0
inputs are low. (Initial state)
IRQ2E
R/W
2
0
7
IRQ1E
to IRQ
R/W
1
0
(Initial state)
0
inputs.
IRQ0E
R/W
0
0
7
71
to