HD64F3437STF16V Renesas Electronics America, HD64F3437STF16V Datasheet - Page 328

• Manufacturer Part Number: HD64F3437STF16V
• Description: MCU 3/5V 60K PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300r

Specifications of HD64F3437STF16V

• Core Processor: H8/300
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: Host Interface, I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

13.2.6
STCR is an 8-bit readable/writable register that controls the SCI operating mode and selects the
TCNT clock source in the 8-bit timers. STCR is initialized to H'00 by a reset and in hardware
standby mode.
Bit 7—I
SCL and SDA. Used when an I
Bit 7: IICS
0
1
Bit 6—I
initial value is 0.
Bit 5—I
ICCR, selects the transfer rate in master mode. For details regarding the transfer rate, refer to
section 13.2.4, I
Bit 4—I
ICSR, ICDR, ICMR/SAR) of the I
Bit 4: IICE
0
1
Bit 3—Slave Input Switch (STAC): Switches host interface input pins. For details, see section
14, Host Interface.
Bit 2—Multiprocessor Enable (MPE): Enables or disables the multiprocessor communication
function on channels SCI0 and SCI1. For details, see section 12, Serial Communication Interface.
Bits 1 and 0—Internal Clock Source Select 1 and 0 (ICKS1, ICSK0): These bits select the
clock input to the timer counters (TCNT) in the 8-bit timers. For details, see section 9, 8-Bit
Timers.
296
Bit
Initial value
Read/Write
2
2
2
2
C Extra Buffer Select (IICS): Makes bits 7 to 4 of port A into output buffers similar to
C Extra Buffer Reserve (IICD): This bit is reserved, but it can be written and read. Its
C Transfer Rate Select (IICX): This bit, in combination with bits CKS2 to CKS0 in
C Master Enable (IICE): Controls CPU access to the data and control registers (ICCR,
Serial/Timer Control Register (STCR)
2
C Bus Control Register (ICCR).
IICS
R/W
Description
PA
PA
Description
CPU access to I
CPU access to I
7
0
7
7
to PA
to PA
IICD
R/W
4
4
6
0
2
are normal input/output pins
are input/output pins that can drive the bus
C bus interface is implemented by software alone.
2
C bus interface.
2
2
C bus interface data and control registers is disabled
C bus interface data and control registers is enabled
IICX
R/W
5
0
IICE
R/W
4
0
STAC
R/W
3
0
MPE
R/W
2
0
ICKS1
R/W
1
0
(Initial value)
(Initial value)
ICKS0
R/W
0
0