HD64F3437STF16V Renesas Electronics America, HD64F3437STF16V Datasheet - Page 303

• Manufacturer Part Number: HD64F3437STF16V
• Description: MCU 3/5V 60K PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300r

Specifications of HD64F3437STF16V

• Core Processor: H8/300
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: Host Interface, I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Transmitting Multiprocessor Serial Data: See figures 12.5 and 12.6.
Receiving Multiprocessor Serial Data: Follow the procedure in figure 12.10 for receiving
multiprocessor serial data.
1
2
3
4
Read receive data from RDR
Read receive data from RDR
Set MPIE bit to 1 in SCR
Read ORER and FER
Read RDRF bit in SSR
Read ORER and FER
Read RDRF bit in SSR
Figure 12.10 Sample Flowchart for Receiving Multiprocessor Serial Data
Clear RE to 0 in SCR
Start receiving
ORER = 1?
ORER = 1?
bits in SSR
bits in SSR
RDRF = 1?
RDRF = 1?
receiving?
Own ID?
Finished
Initialize
FER
FER +
End
Yes
Yes
No
Yes
Yes
No
Yes
No
No
Yes
No
No
Error handling
5
1.
2.
3.
4.
5.
SCI initialization: the receive data function of the RxD pin is
selected automatically.
ID receive cycle: Set the MPIE bit in the serial control register
(SCR) to 1.
SCI status check and ID check: read the serial status register
(SSR), check that RDRF is set to 1, then read receive data
from the receive data register (RDR) and compare with the
processor’s own ID. Transition of the RDRF bit from 0 to
1 can be reported by an RXI interrupt. If the ID does not match
the receive data, set MPIE to 1 again and clear RDRF to 0.
If the ID matches the receive data, clear RDRF to 0.
SCI status check and data receiving: read SSR, check that
RDRF is set to 1, then read data from the receive data register
(RDR) and write 0 in the RDRF bit. Transition of the RDRF bit
from 0 to 1 can be reported by an RXI interrupt.
Receive error handling and break detection: if a receive error
occurs, read the ORER and FER bits in SSR to identify the error.
After executing the necessary error handling, clear both ORER
and FER to 0. Receiving cannot resume while ORER or FER
remains set to 1. When a framing error occurs, the RxD pin
can be read to detect the break state.
Start error handling
process error, and
Discriminate and
clear flags
FER = 1?
Return
No
Yes
Break?
No
Clear RE bit to
0 in SCR
End
Yes
271