HD64F3437STF16V Renesas Electronics America, HD64F3437STF16V Datasheet - Page 193

• Manufacturer Part Number: HD64F3437STF16V
• Description: MCU 3/5V 60K PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300r

Specifications of HD64F3437STF16V

• Core Processor: H8/300
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: Host Interface, I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Similarly, when the BUFEB bit in TCR is set to 1, ICRD is used as a buffer register for ICRB.
When input capture is buffered, if the two input edge bits are set to different values (IEDGA
IEDGC or IEDGB IEDGD), then input capture is triggered on both the rising and falling edges
of the FTIA or FTIB input signal. If the two input edge bits are set to the same value (IEDGA =
IEDGC or IEDGB = IEDGD), then input capture is triggered on only one edge. See table 8.3.
Table 8.3
IEDGA
0
1
Because the input capture registers are 16-bit registers, a temporary register (TEMP) is used when
they are read. See section 8.3, CPU Interface, for details.
To ensure input capture, the width of the input capture pulse should be at least 1.5 system clock
periods (1.5·ø). When triggering is enabled on both edges, the input capture pulse width should be
at least 2.5 system clock periods.
The input capture registers are initialized to H'0000 by a reset and in the standby modes.
Buffered Input Capture Edge Selection (Example)
IEDGC
0
1
0
1
Input Capture Edge
Captured on falling edge of input capture A (FTIA)
Captured on both rising and falling edges of input capture A (FTIA)
Captured on rising edge of input capture A (FTIA)
(Initial value)
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