HD64F3437STF16V Renesas Electronics America, HD64F3437STF16V Datasheet - Page 90

MCU 3/5V 60K PB-FREE 100-TQFP

HD64F3437STF16V

Manufacturer Part Number
HD64F3437STF16V
Description
MCU 3/5V 60K PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300r
Datasheet

Specifications of HD64F3437STF16V

Core Processor
H8/300
Core Size
8-Bit
Speed
16MHz
Connectivity
Host Interface, I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
74
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F3437STF16V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD64F3437STF16V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
3.2
The system control register (SYSCR) is an 8-bit register that controls the operation of the chip.
Bit 7—Software Standby (SSBY): Enables transition to the software standby mode. For details,
see section 22, Power-Down State.
On recovery from software standby mode by an external interrupt, the SSBY bit remains set to 1.
It can be cleared by writing 0.
Bit 7: SSBY
0
1
Bits 6 to 4—Standby Timer Select 2 to 0 (STS2 to STS0): These bits select the clock settling
time when the chip recovers from the software standby mode by an external interrupt. During the
selected time the CPU and on-chip supporting modules continue to stand by. These bits should be
set according to the clock frequency so that the settling time is at least 8 ms. For specific settings,
see section 22.3.3, Clock Settling Time for Exit from Software Standby Mode.
Bit 6: STS2
0
1
58
Bit
Initial value
Read/Write
ZTAT and Mask ROM Versions
System Control Register (SYSCR)
Bit 5: STS1
0
1
0
1
SSBY
R/W
Description
The SLEEP instruction causes a transition to sleep mode.
The SLEEP instruction causes a transition to software standby mode.
7
0
STS2
R/W
6
0
Bit 4: STS0
0
1
0
1
STS1
R/W
5
0
STS0
R/W
4
0
Description
Settling time = 8,192 states
Settling time = 16,384 states
Settling time = 32,768 states
Settling time = 65,536 states
Settling time = 131,072 states
Unused
XRST
3
1
R
NMIEG
R/W
2
0
R/W
HIE
1
0
(Initial value)
(Initial value)
RAME
R/W
0
1

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