HD64F3437STF16V Renesas Electronics America, HD64F3437STF16V Datasheet - Page 271

MCU 3/5V 60K PB-FREE 100-TQFP

HD64F3437STF16V

Manufacturer Part Number
HD64F3437STF16V
Description
MCU 3/5V 60K PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300r
Datasheet

Specifications of HD64F3437STF16V

Core Processor
H8/300
Core Size
8-Bit
Speed
16MHz
Connectivity
Host Interface, I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
74
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F3437STF16V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD64F3437STF16V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Bit 5—Parity Enable (PE): This bit selects whether to add a parity bit in asynchronous mode.
It is ignored in synchronous mode, and when a multiprocessor format is used.
Bit 5: PE
0
1
Bit 4—Parity Mode (O/E ): In asynchronous mode, when parity is enabled (PE = 1), this bit
selects even or odd parity.
Even parity means that a parity bit is added to the data bits for each character to make the total
number of 1’s even. Odd parity means that the total number of 1’s is made odd.
This bit is ignored when PE = 0, or when a multiprocessor format is used. It is also ignored in
synchronous mode.
Bit 4: O/E
0
1
Bit 3—Stop Bit Length (STOP): This bit selects the number of stop bits. It is ignored in
synchronous mode.
Bit 3: STOP
0
1
Description
Transmit: No parity bit is added.
Receive: Parity is not checked.
Transmit: A parity bit is added.
Receive: Parity is checked.
Description
Even parity
Odd parity
Description
One stop bit
Transmit: One stop bit is added.
Receive: One stop bit is checked to detect framing errors.
Two stop bits
Transmit: Two stop bits are added.
Receive: The first stop bit is checked to detect framing errors. If the second
stop bit is a space (0), it is regarded as the next start bit.
(Initial value)
(Initial value)
(Initial value)
239

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