HD64F3437STF16V Renesas Electronics America, HD64F3437STF16V Datasheet - Page 258

• Manufacturer Part Number: HD64F3437STF16V
• Description: MCU 3/5V 60K PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300r

Specifications of HD64F3437STF16V

• Core Processor: H8/300
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: Host Interface, I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

11.2.3
Only bit 3 is described here. For details of other bits, see section 3.2., System Control Register
(SYSCR), and descriptions of the relevant modules.
Bit 3—External Reset (XRST): Indicates the reset source. When the watchdog timer is used, a
reset can be generated by watchdog timer overflow as well as by external reset input.
XRST is a read-only bit. It is set to 1 by an external reset and cleared to 0 by an internal reset due
to watchdog timer overflow when the RST/NMI bit is 1.
Bit 3: XRST
0
1
11.2.4
The watchdog timer’s TCNT and TCSR registers are more difficult to write to than other registers.
The procedures for writing and reading these registers are given below.
Writing to TCNT and TCSR: Word access is required. Byte data transfer instructions cannot be
used for write access.
The TCNT and TCSR registers have the same write address. The write data must be contained in
the lower byte of a word written at this address. The upper byte must contain H'5A (password for
TCNT) or H'A5 (password for TCSR). See figure 11.2. The result of the access depicted in figure
11.2 is to transfer the write data from the lower byte to TCNT or TCSR.
226
Bit
Initial value
Read/Write
System Control Register (SYSCR)
Register Access
Writing to TCNT
Writing to TCSR
SSBY
R/W
Description
A reset is generated by an internal reset due to watchdog timer overflow
A reset is generated by external reset input
7
0
Figure 11.2 Writing to TCNT and TCSR
STS2
R/W
6
0
H'FFA8
H'FFA8
STS1
R/W
5
0
15
15
STS0
R/W
4
0
H'5A
H'A5
XRST
3
1
R
8 7
8 7
Write data
Write data
NMIEG
R/W
2
0
0
0
R/W
HIE
1
0
(Initial value)
RAME
R/W
0
1