HD64F3437STF16V Renesas Electronics America, HD64F3437STF16V Datasheet - Page 196

• Manufacturer Part Number: HD64F3437STF16V
• Description: MCU 3/5V 60K PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300r

Specifications of HD64F3437STF16V

• Core Processor: H8/300
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: Host Interface, I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

8.2.5
Note: * Software can write a 0 in bits 7 to 1 to clear the flags, but cannot write a 1 in these bits.
TCSR is an 8-bit readable and partially writable register that contains the seven interrupt flags and
specifies whether to clear the counter on compare-match A (when the FRC and OCRA values
match).
TCSR is initialized to H'00 by a reset and in the standby modes.
Timing is described in section 8.4, Operation.
Bit 7—Input Capture Flag A (ICFA): This status bit is set to 1 to flag an input capture A event.
If BUFEA = 0, ICFA indicates that the FRC value has been copied to ICRA. If BUFEA = 1, ICFA
indicates that the old ICRA value has been moved into ICRC and the new FRC value has been
copied to ICRA.
ICFA must be cleared by software. It is set by hardware, however, and cannot be set by software.
Bit 7: ICFA
0
1
Bit 6—Input Capture Flag B (ICFB): This status bit is set to 1 to flag an input capture B event.
If BUFEB = 0, ICFB indicates that the FRC value has been copied to ICRB. If BUFEB = 1, ICFB
indicates that the old ICRB value has been moved into ICRD and the new FRC value has been
copied to ICRB.
ICFB must be cleared by software. It is set by hardware, however, and cannot be set by software.
Bit 6: ICFB
0
1
164
Bit
Initial value
Read/Write
Timer Control/Status Register (TCSR)
R/(W)*
ICFA
Description
To clear ICFA, the CPU must read ICFA after it has been set to 1, then write a
0 in this bit.
This bit is set to 1 when an FTIA input signal causes the FRC value to be
copied to ICRA.
Description
To clear ICFB, the CPU must read ICFB after it has been set to 1, then write a
0 in this bit.
This bit is set to 1 when an FTIB input signal causes the FRC value to be
copied to ICRB.
7
0
R/(W)*
ICFB
6
0
R/(W)*
ICFC
5
0
R/(W)*
ICFD
4
0
R/(W)*
OCFA
3
0
R/(W)*
OCFB
2
0
R/(W)*
OVF
1
0
(Initial value)
(Initial value)
CCLRA
R/W
0
0