HD64F3437STF16V Renesas Electronics America, HD64F3437STF16V Datasheet - Page 320

• Manufacturer Part Number: HD64F3437STF16V
• Description: MCU 3/5V 60K PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300r

Specifications of HD64F3437STF16V

• Core Processor: H8/300
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: Host Interface, I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Bit 0—Format Select (FS): Selects whether to use the addressing format or non-addressing
format in slave mode. The addressing format is used to recognize slave addresses.
Bit 0: FS
0
1
13.2.3
ICMR is an 8-bit readable/writable register that selects whether the MSB or LSB is transferred
first, performs wait control, and selects the transfer bit count. ICMR is assigned to the same
address as SAR. ICMR can be written and read only when the ICE bit is set to 1 in ICCR.
ICMR is initialized to H'38 by a reset and in hardware standby mode.
Bit 7—MSB-First/LSB-First Select (MLS): Selects whether data is transferred MSB-first or
LSB-first.
Bit 7: MLS
0
1
Bit 6—Wait Insertion Bit (WAIT): Selects whether to insert a wait between the transfer of data
and the acknowledge bit, in acknowledgement mode. When WAIT is set to 1, after the fall of the
clock for the final data bit, a wait state begins (with SCL staying at the low level). When bit IRIC
is cleared in ICSR, the wait ends and the acknowledge bit is transferred. If WAIT is cleared to 0,
data and acknowledge bits are transferred consecutively with no wait inserted.
Bit 6: WAIT
0
1
288
Bit
Initial value
Read/Write
I
2
C Bus Mode Register (ICMR)
MLS
R/W
Description
Addressing format, slave addresses recognized
Non-addressing format
Description
MSB-first
LSB-first
Description
Data and acknowledge transferred consecutively
Wait inserted between data and acknowledge
7
0
WAIT
R/W
6
0
—
—
5
1
—
—
4
1
—
—
3
1
BC2
R/W
2
0
BC1
R/W
1
0
(Initial value)
(Initial value)
(Initial value)
BC0
R/W
0
0