HD64F3437STF16V Renesas Electronics America, HD64F3437STF16V Datasheet - Page 159

• Manufacturer Part Number: HD64F3437STF16V
• Description: MCU 3/5V 60K PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300r

Specifications of HD64F3437STF16V

• Core Processor: H8/300
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: Host Interface, I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Port 5 Data Direction Register (P5DDR)
P5DDR is an 8-bit register that controls the input/output direction of each pin in port 5. A pin
functions as an output pin if the corresponding P5DDR bit is set to 1, and as an input pin if this bit
is cleared to 0.
P5DDR is a write-only register. Read data is invalid. If read, all bits always read 1.
P5DDR is initialized to H'F8 by a reset and in hardware standby mode. In software standby mode
it retains its existing values, so if a transition to software standby mode occurs while a P5DDR bit
is set to 1, the corresponding pin remains in the output state.
If a transition to software standby mode occurs while port 5 is being used by the SCI, the SCI will
be initialized, so the pin will revert to general-purpose input/output, controlled by P5DDR and
P5DR.
Port 5 Data Register (P5DR)
P5DR is an 8-bit register that stores data for pins P5
be modified, and are always read as 1.
When a P5DDR bit is set to 1, if port 5 is read, the value in P5DR is obtained directly, regardless
of the actual pin state. When a P5DDR bit is cleared to 0, if port 5 is read the pin state is obtained.
This also applies to pins used as SCI pins.
P5DR is initialized to H'F8 by a reset and in hardware standby mode. In software standby mode it
retains its existing values.
Bit
Initial value
Read/Write
Bit
Initial value
Read/Write
—
—
—
—
7
1
7
1
—
—
—
—
6
1
6
1
—
—
—
—
5
1
5
1
—
—
—
—
4
1
4
1
2
to P5
0
. Bits 7 to 3 are reserved. They cannot
—
—
—
—
3
1
3
1
P5
R/W
P5
2
W
2
DDR P5
0
2
0
2
R/W
P5
1
W
1
DDR P5
0
1
0
1
R/W
P5
0
W
0
DDR
0
0
0
0
127