HD64F3437STF16V Renesas Electronics America, HD64F3437STF16V Datasheet - Page 371

• Manufacturer Part Number: HD64F3437STF16V
• Description: MCU 3/5V 60K PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300r

Specifications of HD64F3437STF16V

• Core Processor: H8/300
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: Host Interface, I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

15.2
15.2.1
Bits 15 to 6—A/D Conversion Data (AD9 to AD0): 10-bit data giving an A/D conversion result.
Bits 5 to 0—Reserved: These bits cannot be modified and are always read as 0.
The four A/D data registers (ADDRA to ADDRD) are 16-bit read-only registers that store the
results of A/D conversion.
An A/D conversion produces 10-bit data, which is transferred for storage into the A/D data
register corresponding to the selected channel. The upper 8 bits of the result are stored in the upper
byte of the A/D data register. The lower 2 bits are stored in the lower byte. Bits 5 to 0 of an A/D
data register are reserved bits that always read 0. Table 15.3 indicates the pairings of analog input
channels and A/D data registers.
The CPU can always read the A/D data registers. The upper byte can be read directly, but the
lower byte is read through a temporary register (TEMP). For details see section 15.3, CPU
Interface.
The A/D data registers are initialized to H'0000 by a reset and in standby mode.
Table 15.3 Analog Input Channels and A/D Data Registers
Group 0
AN
AN
AN
AN
Bit
ADDRn
Initial value
Read/Write
0
1
2
3
Analog Input Channel
Register Descriptions
A/D Data Registers A to D (ADDRA to ADDRD)
AD9 AD8 AD6 AD5 AD4 AD3 AD2 AD1 AD0 —
15
R
Group 1
AN
AN
AN
AN
0
4
5
6
7
14
R
0
13
R
0
12
R
0
A/D Data Register
ADDRA
ADDRB
ADDRC
ADDRD
11
R
0
10
R
0
R
9
0
R
8
0
R
7
0
R
6
0
—
R
5
0
—
R
4
0
—
R
3
0
—
R
2
0
—
R
1
0
339
—
R
0
0