HD64F3437STF16V Renesas Electronics America, HD64F3437STF16V Datasheet - Page 310

• Manufacturer Part Number: HD64F3437STF16V
• Description: MCU 3/5V 60K PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300r

Specifications of HD64F3437STF16V

• Core Processor: H8/300
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: Host Interface, I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Transmitting and Receiving Serial Data Simultaneously: Follow the procedure in figure 12.17
for transmitting and receiving serial data simultaneously. If clock output mode is selected, output
of the serial clock begins simultaneously with serial transmission.
278
1
2
3
5
Note: In switching from transmitting or receiving to simultaneous transmitting and receiving, clear both
No
in TDR and clear TDRE
Read ORER bit in SSR
Read RDRF bit in SSR
TE and RE to 0, then set TE and RE to 1 simultaneously using an MOV instruction. Do not use a
BEST instruction for this purpose.
Read TDRE bit in SSR
RDRF bit to 0 in SSR
Clear TE and RE bits
from RDR and clear
Write transmit data
Figure 12.17 Sample Flowchart for Serial Transmitting and Receiving
Read receive data
transmitting and
bit to 0 in SSR
ORER = 1?
to 0 in SCR
TDRE = 1?
RDRF = 1?
receiving?
Initialize
End of
Start
End
Yes
No
Yes
Yes
No
Yes
No
Error handling
4
1.
2.
3.
4.
5.
SCI initialization: the transmit data output function of
the TxD pin and receive data input function of the
RxD pin are selected, enabling simultaneous
transmitting and receiving.
SCI status check and transmit data write: read the
serial status register (SSR), check that the TDRE bit
is 1, then write transmit data in the transmit data
register (TDR) and clear TDRE to 0. Transition of the
TDRE bit from 0 to 1 can be reported by a TXI interrupt.
SCI status check and receive data read: read the
serial status register (SSR), check that the RDRF
bit is 1, then read receive data from the receive data
register (RDR) and clear RDRF to 0. Transition of
the RDRF bit from 0 to 1 can be reported by an RXI
interrupt.
Receive error handling: if a receive error occurs, read
the ORER bit in SSR then, after executing the
necessary error handling, clear ORER to 0. Neither
transmitting nor receiving can resume while ORER
remains set to 1.
To continue transmitting and receiving serial data:
read RDR and clear RDRF to 0 before the MSB
(bit 7) of the current frame is received. Also read the
TDRE bit and check that it is set to 1, indicating that
it is safe to write; then write data in TDR and clear
TDRE to 0 before the MSB (bit 7) of the current frame
is transmitted.