HD64F3437STF16V Renesas Electronics America, HD64F3437STF16V Datasheet - Page 394

• Manufacturer Part Number: HD64F3437STF16V
• Description: MCU 3/5V 60K PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300r

Specifications of HD64F3437STF16V

• Core Processor: H8/300
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: Host Interface, I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

17.1.2
The on-chip RAM is enabled or disabled by the RAME bit in SYSCR. See section 3.2, System
Control Register (SYSCR), for the other SYSCR bits.
Bit 0—RAM Enable (RAME): This bit enables or disables the on-chip RAM. The RAME bit is
initialized to 1 on the rising edge of the RES signal. The RAME bit is not initialized in software
standby mode.
Bit 0: RAME
0
1
17.2
17.2.1
If the RAME bit is set to 1, accesses to addresses H'F780 to H'FF7F in the H8/3437 and H8/3436
and addresses H'FB80 to H'FF7F in the H8/3434 are directed to the on-chip RAM. If the RAME
bit is cleared to 0, accesses to these addresses are directed to the external data bus.
17.2.2
If the RAME bit is set to 1, accesses to addresses H'F780 to H'FF7F in the H8/3437 and H8/3436
and addresses H'FB80 to H'FF7F in the H8/3434 are directed to the on-chip RAM.
If the RAME bit is cleared to 0, the on-chip RAM data cannot be accessed. Attempted write access
has no effect. Attempted read access always results in H'FF data being read.
Notes: 1. When V
362
Bit
Initial value
Read/Write
2. On-chip RAM values are not guaranteed if power is turned off, then on again, in any
3. When specific bits in RAM are used as control bits, initial values must be set after
RAM Enable Bit (RAME) in System Control Register (SYSCR)
Operation
Expanded Modes (Modes 1 and 2)
Single-Chip Mode (Mode 3)
See section 21.4.1 and Appendix E for details.
state.
powering on.
SSBY
R/W
CC
Description
On-chip RAM is disabled.
On-chip RAM is enabled.
7
0
V
RAM
STS2
R/W
, on-chip RAM values can be retained by using the specified method.
6
0
STS1
R/W
5
0
STS0
R/W
4
0
XRST
3
1
R
NMIEG
R/W
2
0
R/W
HIE
1
0
(Initial value)
RAME
R/W
0
1