HD64F3437STF16V Renesas Electronics America, HD64F3437STF16V Datasheet - Page 668

MCU 3/5V 60K PB-FREE 100-TQFP

HD64F3437STF16V

Manufacturer Part Number
HD64F3437STF16V
Description
MCU 3/5V 60K PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300r
Datasheet

Specifications of HD64F3437STF16V

Core Processor
H8/300
Core Size
8-Bit
Speed
16MHz
Connectivity
Host Interface, I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
74
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F3437STF16V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD64F3437STF16V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
SSR—Serial Status Register
636
Note: * Software can write a 0 in bits 7 to 3 to clear the flags, but cannot write a 1 in these bits.
Bit
Initial value
Read/Write
Transmit Data Register Empty
0
1
Cleared by reading TDRE = 1, then writing 0 in TDRE.
Set when:
1. Data is transferred from TDR to TSR.
2. TE is cleared while TDRE = 0.
Receive Data Register Full
0
1
Cleared by reading RDRF = 1, then writing 0 in RDRF.
Set when one character is received normally and transferred from RSR to RDR.
Overrun Error
TDRE
0
1
R/(W)
7
1
Cleared by reading ORER = 1, then writing 0 in ORER.
Set when an overrun error occurs (next data is completely
received while RDRF bit is set to 1).
*
Framing Error
0
1
RDRF
R/(W)
Cleared by reading FER = 1, then writing 0 in FER.
Set when a framing error occurs (stop bit is 0).
6
0
Parity Error
0
1
*
Cleared by reading PER = 1, then writing 0 in PER.
Set when a parity error occurs (parity of receive data
does not match parity selected by O/E bit in SMR).
ORER
R/(W)
5
0
Transmit End
0
1
*
Cleared by reading TDRE = 1, then writing 0 in TDRE.
Set to 1 when TE = 0, or when TDRE = 1 at the end of
character transmission.
R/(W)
Multiprocessor Bit
FER
0
1
4
0
Multiprocessor bit = 0 in receive data.
Multiprocessor bit = 1 in receive data.
*
Multiprocessor Bit Transfer
0
1
R/(W)
PER
3
0
Multiprocessor bit = 0 in transmit data.
Multiprocessor bit = 1 in transmit data.
H'8C
*
TEND
R
2
1
MPB
R
1
0
MPBT
R/W
0
0
SCI1

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