HD64F3437STF16V Renesas Electronics America, HD64F3437STF16V Datasheet - Page 179

• Manufacturer Part Number: HD64F3437STF16V
• Description: MCU 3/5V 60K PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300r

Specifications of HD64F3437STF16V

• Core Processor: H8/300
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: Host Interface, I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Port A Data Direction Register (PADDR)
PADDR is an 8-bit register that controls the input/output direction of each pin in port A. A pin
functions as an output pin if the corresponding PADDR bit is set to 1, and as an input pin if this bit
is cleared to 0.
PADDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode
it retains its existing values, so if a transition to software standby mode occurs while a PADDR bit
is set to 1, the corresponding pin remains in the output state.
Port A Output Data Register (PAODR)
PAODR is an 8-bit register that stores data for pins PA
and read, regardless of the PADDR settings.
PAODR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode
it retains its existing values.
Port A Input Data Register (PAPIN)
Note: * Depends on the levels of pins PA
When PAPIN is read, the pin states are always read.
Bit
Initial value
Read/Write
Bit
Initial value
Read/Write
Bit
Initial value
Read/Write
PA
R/W
PA
PA
—*
7
W
7
0
7
0
7
R
DDR PA
7
7
R/W
PA
PA
—*
6
W
6
0
6
0
6
R
DDR PA
6
6
R/W
PA
PA
—*
7
5
W
5
0
5
0
5
R
DDR PA
to PA
5
5
0
.
R/W
PA
PA
—*
4
W
4
0
4
0
4
R
DDR PA
4
4
7
to PA
R/W
PA
PA
—*
3
W
3
0
3
0
0
3
R
DDR PA
. PAODR can always be written to
3
3
R/W
PA
PA
—*
2
W
2
0
2
0
2
R
DDR PA
2
2
R/W
PA
PA
—*
1
W
1
0
1
0
1
R
DDR PA
1
1
R/W
PA
PA
—*
0
W
0
0
0
0
0
R
DDR
0
0
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