HD64F3437STF16V Renesas Electronics America, HD64F3437STF16V Datasheet - Page 300

• Manufacturer Part Number: HD64F3437STF16V
• Description: MCU 3/5V 60K PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300r

Specifications of HD64F3437STF16V

• Core Processor: H8/300
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: Host Interface, I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

In receiving, the SCI operates as follows.
1. The SCI monitors the receive data line and synchronizes internally when it detects a start bit.
2. Receive data is shifted into RSR in order from LSB to MSB.
3. The parity bit and stop bit are received.
Note: When a receive error flag is set, further receiving is disabled. The RDRF bit is not set to 1.
4. After setting RDRF to 1, if the RIE bit (receive-end interrupt enable) is set to 1 in SCR, the
Table 12.10 Receive Error Conditions and SCI Operation
Receive Error
Overrun error
Framing error
Parity error
268
After receiving these bits, the SCI makes the following checks:
a. Parity check: The number of 1s in the receive data must match the even or odd parity
b. Stop bit check: The stop bit value must be 1. If there are two stop bits, only the first stop bit
c. Status check: RDRF must be 0 so that receive data can be loaded from RSR into RDR.
If these checks all pass, the SCI sets RDRF to 1 and stores the received data in RDR. If one of
the checks fails (receive error), the SCI operates as indicated in table 12.10.
SCI requests an RXI (receive-end) interrupt. If one of the error flags (ORER, PER, or FER) is
set to 1 and the RIE bit in SCR is also set to 1, the SCI requests an ERI (receive-error)
interrupt.
setting of the O/E bit in SMR.
is checked.
Be sure to clear the error flags.
Abbreviation
ORER
FER
PER
Condition
Receiving of next data ends
while RDRF is still set to 1
in SSR
Stop bit is 0
Parity of receive data differs
from even/odd parity setting
in SMR
Data Transfer
Receive data not loaded from
RSR into RDR
Receive data loaded from
RSR into RDR
Receive data loaded from
RSR into RDR