HD64F3437STF16V Renesas Electronics America, HD64F3437STF16V Datasheet - Page 106

• Manufacturer Part Number: HD64F3437STF16V
• Description: MCU 3/5V 60K PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300r

Specifications of HD64F3437STF16V

• Core Processor: H8/300
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: Host Interface, I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

4.3.3
The nine external interrupts are NMI and IRQ
used to recover from software standby mode.
NMI: A nonmaskable interrupt is generated on the rising or falling edge of the NMI input signal
regardless of whether the I (interrupt mask) bit is set in the CCR. The valid edge is selected by the
NMIEG bit in the system control register. The NMI vector number is 3. In the NMI hardware
exception-handling sequence the I bit in the CCR is set to 1.
IRQ
as selected by ISCR bits IRQ0SC to IRQ7SC. These interrupts can be masked collectively by the I
bit in the CCR, and can be enabled and disabled individually by setting and clearing bits IRQ0E to
IRQ7E in the IRQ enable register.
The IRQ
KEYIN
corresponding KMIMR bits should be cleared to 0 to enable the corresponding key sense input
interrupts. KMIMR bits corresponding to unused key sense inputs should be set to 1 to disable the
interrupts. All 16 key sense interrupts are combined into a single IRQ
When one of these interrupts is accepted, the I bit is set to 1. IRQ
numbers 4 to 11. They are prioritized in order from IRQ
table 4.2.
Interrupts IRQ
When using external interrupts IRQ
pins to the input state, and do not use these pins as input or output pins for the timers, serial
communication interface, I
4.3.4
Twenty-six internal interrupts can be requested by the on-chip supporting modules. Each interrupt
source has its own vector number, so the interrupt-handling routine does not have to determine
which interrupt has occurred. All internal interrupts are masked when the I bit in the CCR is set to
1. When one of these interrupts is accepted, the I bit is set to 1 to mask further interrupts (except
NMI). The vector numbers are 12 to 37. For the priority order, see table 4.2.
74
0
to IRQ
0
6
to KEYIN
External Interrupts
Internal Interrupts
input signal can be logically ORed internally with the key sense input signals. When
7
: These interrupt signals are level-sensed or sensed on the falling edge of the input,
0
to IRQ
15
pins (P6
7
do not depend on whether pins IRQ
2
C bus interface, host interface, or A/D converter.
0
to P6
0
7
to IRQ
and PA
7
, clear the corresponding DDR bits to 0 to set these
0
0
to PA
to IRQ
7
) are used for key sense input, the
7
. NMI, IRQ
7
(low) to IRQ
0
to IRQ
0
to IRQ
0
, IRQ
7
6
are input or output pins.
0
interrupt.
(high). For details, see
1
7
, IRQ
have interrupt vector
2
, and IRQ
6
can be