HD64F3437STF16V Renesas Electronics America, HD64F3437STF16V Datasheet - Page 208

MCU 3/5V 60K PB-FREE 100-TQFP

HD64F3437STF16V

Manufacturer Part Number
HD64F3437STF16V
Description
MCU 3/5V 60K PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300r
Datasheet

Specifications of HD64F3437STF16V

Core Processor
H8/300
Core Size
8-Bit
Speed
16MHz
Connectivity
Host Interface, I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
74
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F3437STF16V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD64F3437STF16V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
8.4.3
If the CCLRA bit in TCSR is set to 1, the FRC is cleared when compare-match A occurs. Figure
8.7 shows the timing of this operation.
8.4.4
Input Capture Timing: An internal input capture signal is generated from the rising or falling
edge of the signal at the input capture pin FTIx (x = A, B, C, D), as selected by the corresponding
IEDGx bit in TCR. Figure 8.8 shows the usual input capture timing when the rising edge is
selected (IEDGx = 1).
If the upper byte of ICRA/B/C/D is being read when the corresponding input capture signal
arrives, the internal input capture signal is delayed by one state. Figure 8.9 shows the timing for
this case.
176
ø
Internal compare-
match A signal
FRC
ø
Input data
FTI pin
Internal input
capture signal
FRC Clear Timing
Input Capture Timing
Figure 8.7 Clearing of FRC by Compare-Match A
Figure 8.8 Input Capture Timing (Usual Case)
N
H'0000

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