UPD70F3785GJ-GAE-AX Renesas Electronics America, UPD70F3785GJ-GAE-AX Datasheet - Page 1114
UPD70F3785GJ-GAE-AX
Manufacturer Part Number
UPD70F3785GJ-GAE-AX
Description
MCU 32BIT V850ES/JX3-E 144-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Er
Datasheet
1.UPD70F3778GF-GAT-AX.pdf
(1817 pages)
Specifications of UPD70F3785GJ-GAE-AX
Core Processor
RISC
Core Size
32-Bit
Speed
50MHz
Connectivity
CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
100
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
124K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Manufacturer
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Company:
Part Number:
UPD70F3785GJ-GAE-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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21.7 Bit Set/Clear Function
interface. An operation error occurs if the following registers are written directly. Do not write any values directly via
bit manipulation, read/modify/write, or direct writing of target values.
25 below to set or clear the lower 8 bits in these registers.
the bit status after set/clear operation is specified in Figure 21-26). Figure 21-25 shows how the values of set bits or
clear bits relate to set/clear/no change operations in the corresponding register.
1112
The CAN control registers include registers whose bits can be set or cleared via the CPU and via the CAN
• CAN0 global control register (C0GMCTRL)
• CAN0 global automatic block transmission control register (C0GMABT)
• CAN0 module control register (C0CTRL)
• CAN0 module interrupt enable register (C0IE)
• CAN0 module interrupt status register (C0INTS)
• CAN0 module receive history list register (C0RGPT)
• CAN0 module transmit history list register (C0TGPT)
• CAN0 module time stamp register (C0TS)
• CAN0 message control register (C0MCTRLm)
Remark m = 00 to 31
All the 16 bits in the above registers can be read via the usual method. Use the procedure described in Figure 21-
Setting or clearing of lower 8 bits in the above registers is performed in combination with the higher 8 bits (refer to
Register’s current value
Register’s value after
write operation
Write value
Figure 21-25. Example of Bit Setting/Clearing Operations
0
0
0
0
0
0
CHAPTER 21 CAN CONTROLLER
0
0
0
User’s Manual U19601EJ2V0UD
0
0
0
0
1
0
0
0
0
0
1
0
clear 1
set
0
1
0
1
1
0
0
1
1
0
1
0
0
0
0
0
0
1
1
0
1
0
0
1
1
1
0
0
0
0
0
0
0
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1
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