UPD70F3785GJ-GAE-AX Renesas Electronics America, UPD70F3785GJ-GAE-AX Datasheet - Page 186
UPD70F3785GJ-GAE-AX
Manufacturer Part Number
UPD70F3785GJ-GAE-AX
Description
MCU 32BIT V850ES/JX3-E 144-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Er
Datasheet
1.UPD70F3778GF-GAT-AX.pdf
(1817 pages)
Specifications of UPD70F3785GJ-GAE-AX
Core Processor
RISC
Core Size
32-Bit
Speed
50MHz
Connectivity
CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
100
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
124K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Manufacturer
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Price
Company:
Part Number:
UPD70F3785GJ-GAE-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Notes 1. KR0 and TIAB11 are alternate functions. When using the pin for the TIAB11 function, disable key return detection of KR0, which is the alternate function (set
P90
P91
P92
Pin Name
2. When using as the A0 to A15 pins, be sure to set all 16 bits of the PMC9 register to FFFFH at once.
3. KR1 and TIAB10 are alternate functions. When using the pin for the TIAB10 function, disable key return detection of KR1, which is the alternate function (set
4. KR2 and TIAB12 are alternate functions. When using the pin for the TIAB12 function, disable key return detection of KR2, which is the alternate function (set
the KRM.KRM0 bit to 0). Also, when using the pin for the KR0 function, disable edge detection of TIAB11, which is the alternate function (set the
TAB1IOC1.TAB1IS3 and TAB1IS2 bits to 00).
the KRM.KRM1 bit to 0). Also, when using the pin for the KR1 function, disable edge detection of TIAB10, which is the alternate function (set the
TAB1IOC1.TAB1IS1 and TAB1IS0 bits to 00).
the KRM.KRM2 bit to 0). Also, when using the pin for the KR2 function, disable edge detection of TIAB12, which is the alternate function (set the
TAB1IOC1.TAB1IS5 and TAB1IS4 bits to 00).
TOAB1T1
TOAB11
TIAB11
KR0
INTP12
A0
TOAB1B1
TIAB10
KR1
TOAB10
A1
TOAB1T2
TOAB12
TIAB12
KR2
INTP13
A2
Alternate Function
Note 2
Note 2
Note 1
Name
Note 1
Note 3
Note 4
Note 1
Note 3
Note 4
Output
Output
Input
Input
Input
Output
Output
Input
Input
Output
Output
Output
Output
Input
Input
Input
Output
I/O
P90 = Setting not required PM90 = Setting not required PMC90 = 1
P90 = Setting not required PM90 = Setting not required PMC90 = 1
P90 = Setting not required PM90 = Setting not required PMC90 = 1
P90 = Setting not required PM90 = Setting not required PMC90 = 1
P90 = Setting not required PM90 = Setting not required PMC90 = 1
P90 = Setting not required PM90 = Setting not required PMC90 = 1
P91 = Setting not required PM91 = Setting not required PMC91 = 1
P91 = Setting not required PM91 = Setting not required PMC91 = 1
P91 = Setting not required PM91 = Setting not required PMC91 = 1
P91 = Setting not required PM91 = Setting not required PMC91 = 1
P91 = Setting not required PM91 = Setting not required PMC91 = 1
P92 = Setting not required PM92 = Setting not required PMC92 = 1
P92 = Setting not required PM92 = Setting not required PMC92 = 1
P92 = Setting not required PM92 = Setting not required PMC92 = 1
P92 = Setting not required PM92 = Setting not required PMC92 = 1
P92 = Setting not required PM92 = Setting not required PMC92 = 1
P92 = Setting not required PM92 = Setting not required PMC92 = 1
Pn Register
Pnx Bit of
Table 4-18. Using Port Pin as Alternate-Function Pin (7/13)
PMn Register
PMnx Bit of
PMCn Register
PMCnx Bit of
PFCE90 = 0
PFCE90 = 0
PFCE90 = 0
PFCE90 = 0
PFCE90 = 1
PFCE90 = 1
PFCE91 = 0
PFCE91 = 0
PFCE91 = 0
PFCE91 = 1
PFCE91 = 1
PFCE92 = 0
PFCE92 = 0
PFCE92 = 0
PFCE92 = 0
PFCE92 = 1
PFCE92 = 1
PFCEn Register
PFCEnx Bit of
PFC90 = 0
PFC90 = 0
PFC90 = 1
PFC90 = 1
PFC90 = 0
PFC90 = 1
PFC91 = 0
PFC91 = 1
PFC91 = 1
PFC91 = 0
PFC91 = 1
PFC92 = 0
PFC92 = 0
PFC92 = 1
PFC92 = 1
PFC92 = 0
PFC92 = 1
PFCn Register
PFCnx Bit of
KRM0 (KRM) = 0
TAB1TIS3, TAB1TIS2 (TAB1I0C1) = 0
KRM1 (KRM) = 0
TAB1TIS1, TAB1TIS0 (TAB1I0C1) = 0
PF91 (PF9) = 1
KRM2 (KRM) = 0
TAB1TIS5, TAB1TIS4 (TAB1I0C1) = 0
(Registers)
Other Bits
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