UPD70F3785GJ-GAE-AX Renesas Electronics America, UPD70F3785GJ-GAE-AX Datasheet - Page 241

• Manufacturer Part Number: UPD70F3785GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3785GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Cautions 1. External event count input is selected in the external event count mode
TAAnMD2
TAAnEEE
The TAAnEEE bit selects whether counting is performed with the internal count
clock or the valid edge of the external event count input.
0
1
0
0
0
0
1
1
1
1
TAAnMD1
Disables operation with external event count input.
(Performs counting with the count clock selected by the
TAAnCTL0.TAAnCK0 to TAAnCK2 bits.)
CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
Enables operation with external event count input.
(Performs counting at every valid edge of the external event count input
signal.)
2. Set
0
0
1
1
0
0
1
1
regardless of the value of the TAAnEEE bit.
TAAnCTL0.TAAnCE bit = 0. (The same value can be written when the
TAAnCE bit = 1.)
performed with the TAAnCE bit = 1.
performed, clear the TAAnCE bit to 0 and then set the bits again (n = 0 to
5).
TAAnMD0
the
0
1
0
1
0
1
0
1
User’s Manual U19601EJ2V0UD
TAAnEEE
Interval timer mode
External event count mode
External trigger pulse output mode
One-shot pulse output mode
PWM output mode
Free-running timer mode
Pulse width measurement mode
Setting prohibited
Count clock selection
The operation is not guaranteed when rewriting is
and
Timer mode selection
TAAnMD2
to
If rewriting was mistakenly
TAAnMD0
bits
when
the
(2/2)
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